Granted Patent B2

US 9,728,255 · App. 14/882,147 · Granted Aug 8, 2017

Abstract

Claims (35)

1. A memory device comprising:

a planar semiconductor substrate layer;

a planar variable resistance layer disposed above the planar semiconductor substrate layer;

a planar channel layer disposed above the planar variable resistance layer; and

one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage.

2. The memory device of claim 1 , further comprising:

an oxide layer disposed between the planer channel layer and the one or more gates configured to reduce an amount of current flowing from the one or more gates into the planar channel layer.

3. The memory device of claim 1 , further comprising:

a conductive layer disposed between the planar channel layer and the planar variable resistance layer; and

one or more non-conductive plugs positioned within the conductive layer and respectively aligned with the one or more gates.

4. The memory device of claim 3 , wherein a thickness of at least one of the one or more non-conductive plugs is greater than a thickness of the conductive layer.

5. The memory device of claim 3 , wherein the planar variable resistance layer comprises a planar layer of resistive memory, wherein the conductive layer comprises a first conductive material and a second, different, conductive material alternately disposed between the one or more non-conductive plugs.

6. The memory device of claim 1 , wherein:

the respective region of the variable resistance layer is configurable to have a low-resistive state and a high-resistive state,

the respective gate is configured to direct the current into the respective region of the variable resistance layer by causing a resistance of the respective region of the planar channel layer to be greater than a resistance of the high-resistive state of the respective region of the variable resistance layer, and

the respective gate is configured to cause the resistance of the respective region of the planar channel layer to be lesser than a resistance of the low-resistive state of the respective region of the variable resistance layer in response to the voltage applied to the respective gate not being greater than the threshold voltage.

7. The memory device of claim 1 , wherein the planar variable resistance layer comprises a planar layer of phase change memory (PCM).

8. The memory device of claim 1 , wherein the one or more gates comprise at least two gates.

9. The memory device of claim 8 , wherein:

the one or more gates positioned along a length of the memory device comprise a plurality of gates positioned in a grid along the length and a width of the memory device,

a plurality of respective memory cells are defined by a respective gate of the one or more gates, a respective region of the planar channel layer positioned below the respective gate, and a respective region of the variable resistance layer positioned below the respective gate,

a plurality of respective memory cell strings are defined by memory cells of the plurality of memory cells that are positioned along respective parallel lines of the grid,

the memory device further comprises:

a plurality of select switches respectively configured to couple respective memory cell strings of the plurality of respective memory cell strings to respective voltage sources of a plurality of voltage sources; and

one or more decoders configured to determine respective resistances across the plurality of respective memory cell strings.

10. The memory device of claim 9 , wherein the plurality of select switches comprises a first plurality of select switches, the memory device further comprising:

a second plurality of select switches respectively configured to couple respective memory cell strings of the plurality of respective memory cell strings to respective ohmmeters of the one or more ohmmeters.

11. A data storage system comprising:

one or more memory devices comprising:

a planar semiconductor substrate layer;

a planar variable resistance layer disposed above the planar semiconductor substrate layer;

a planar channel layer disposed above the planar variable resistance layer; and

one or more gates positioned along a length of the memory device and above the planar channel layer, wherein each respective gate of the one or more gates is configured to direct at least a portion of a current flowing through a respective region of the planar channel layer positioned below the respective gate into a respective region of the variable resistance layer positioned below the respective gate in response to a voltage applied to the respective gate being greater than a threshold voltage; and

a controller configured to write data to and read data from the one or more memory devices.

12. The memory device of claim 3 , wherein the conductive layer comprises a planar conductive layer.

Assignments (12)