Enhanced solid-state drive write performance with background erase
A method for programming memory blocks in a memory system includes identifying, using at least one memory block characteristic, candidate memory blocks of the memory blocks in the memory system. The method also includes performing a pre-erase operation, using a pre-erase verify level, on the candidate memory blocks. The method also includes storing, on a pre-erase table, pre-erase information for each memory block of the candidate memory blocks. The method also includes identifying, using the pre-erase table, at least one memory block to be programmed. The method also includes programming the at least one memory block by performing a preprogram erase operation on the at least one memory block using the pre-erase verify level, and performing a write operation on the at least one memory block.
1. A method for programming memory blocks in a memory system, the method comprising:
identifying, using at least one memory block characteristic, candidate memory blocks of the memory blocks in the memory system;
performing a pre-erase operation, using a pre-erase verify level, on the candidate memory blocks;
storing, on a pre-erase table, pre-erase information for each memory block of the candidate memory blocks;
identifying, using the pre-erase table, at least one memory block to be programmed; and
programming the at least one memory block by:
performing a preprogram erase operation on the at least one memory block using the pre-erase verify level, and
performing a write operation on the at least one memory block.
2. The method of claim 1 , wherein performing the pre-erase operation, using the pre-erase verify level, includes performing the pre-erase operation during an idle time.
3. The method of claim 1 , wherein the pre-erase information for a respective memory block of the candidate memory blocks includes at least a memory address associated with the respective memory block and an indication that the respective memory block has been pre-erased using the pre-erase verify level.
4. The method of claim 1 , further comprising recording an erase time associated with performing the pre-erase operation on the candidate memory blocks.
5. The method of claim 1 , further comprising recording an erase time associated with performing the preprogram erase operation on the at least one memory block.
6. The method of claim 1 , wherein the at least one memory block characteristic includes a number of program erase cycles associated with each of the candidate memory blocks.
7. The method of claim 1 , wherein the at least one memory block characteristic includes erase times associated with each of the candidate memory blocks.
8. The method of claim 1 , wherein the at least one memory block characteristic includes a bit error rate associated with each of the candidate memory blocks.
9. The method of claim 1 , wherein the pre-erase verify level is greater than 0 volts.
10. The method of claim 1 , wherein a number of erase pulses associated with the preprogram erase operation correspond to the pre-erase verify level.
11. A controller comprising:
a bus interface configured to receive memory block characteristics associated with memory blocks on a free block list; and
a processor configured to:
identify, using at least one memory block characteristic of the memory block characteristics, candidate memory blocks of the memory blocks on the free block list;
perform a pre-erase operation, using a pre-erase verify level, on the candidate memory blocks;
perform a preprogram erase operation on at least one memory block of the candidate memory blocks using the pre-erase verify level, and
perform a write operation on the at least one memory block.
12. The controller of claim 11 , wherein the processor is further configured to performs the pre-erase operation during an idle time.
13. The controller of claim 11 , wherein the processor is further configured to record an erase time associated with performing the pre-erase operation on the candidate memory blocks.
14. The controller of claim 11 , wherein the processor is further configured to record an erase time associated with performing the preprogram erase operation on the at least one memory block.
15. The controller of claim 11 , wherein the at least one memory block characteristic includes a number of program erase cycles associated with each of the candidate memory blocks.
16. The controller of claim 11 , wherein the at least one memory block characteristic includes erase times associated with each of the candidate memory blocks.
17. The controller of claim 11 , wherein the at least one memory block characteristic includes a bit error rate associated with each of the candidate memory blocks.
18. The controller of claim 11 , wherein the pre-erase verify level is greater than 0 volts.
19. The controller of claim 11 , wherein a number of erase pulses associated with the preprogram erase operation correspond to the pre-erase verify level.
20. A method for enhancing performance of write operations of memory blocks, the method comprising:
identifying candidate memory blocks from memory blocks on a free block list using at least one of a program erase cycle value associated with each of the memory blocks on the free block list, an erase time value associated with each of the memory blocks on the free block list, and a bit error rate value associated with each of the memory blocks on the free block list;
performing a pre-erase operation on each of the candidate memory blocks using a pre-erase verify level that is greater than 0 volts;
recording an erase time associated the pre-erase operation; and
storing, for each candidate memory block, a corresponding erase time and the pre-erase verify level.