IP Library Granted Patent US 12,197,323
Granted Patent B2
US 12,197,323 · App. 18/225,789 · Granted Jan 14, 2025

Data storage device with balanced background operations and method therefor

Inventors: Anamika Choudhary (New Delhi, IN); Ramkumar Ramamurthy (Bangalore, IN); Narendhiran Chinnaanangur Ravimohan (Bangalore, IN); Lovish Singla (Bangalore, IN); Meenakshi C (Bangalore, IN); Bhagyashankar Muthu Kumaresan (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06F12/0253G06F12/0246
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Quick Facts
Patent No.
US 12,197,323
App. No.
18/225,789
Granted
Jan 14, 2025
Kind
B2
Abstract

In solid state memory devices, garbage collection can be a bottleneck in meeting stringent performance requirements of certain hosts that generate a relatively-large amount of data (e.g., hosts that generate video data). With such hosts, the performance drop caused by background garbage collection can result in video recording failures. The memory device and method presented herein performs background operations in such a way as to enhance sustained performance. In general, a counter is maintained that reflects an amount of memory written to by a host, as well as an amount of memory freed by garbage collection operations. Each step of a garbage collection operation can be performed in response to a value of the counter being greater than a threshold for the step such that there is a balance between memory written and memory freed.

Claims (39)

1. A data storage device comprising:

a memory; and

a processor coupled with the memory and configured to:

determine a number of pages of the memory that have been written to by a host;

in response to the number of pages that have been written to by the host being above a first threshold, move a page of data from a source block in the memory to a destination block in the memory as part of a garbage collection operation;

in response to the number of pages in the source block that have been written to by the host being above a second threshold, verify that the page of data from the source block was successfully written to the destination block; and

in response to the number of pages in the source block that have been written to by the host being above a third threshold, update a logical-to-physical address map to reflect that the page of data was successfully written to the destination block;

wherein the first, second, and third thresholds comprise different weighted ratios of a valid fragment count in the source block to an invalid fragment count in the source block.

2. The data storage device of claim 1 , wherein a number of blocks freed by the garbage collection operation equals a sum of a number of blocks used to store valid data relocated by the garbage collection operation and a number of blocks used to store incoming host data.

3. The data storage device of claim 1 , wherein the processor is further configured to determine the different weighted ratios by calculating a quotient of the valid fragment count divided by a difference between a maximum valid fragment count and the valid fragment count.

4. The data storage device of claim 1 , wherein a weightage of each weighted ratio is based on an incoming write length of host data.

5. The data storage device of claim 1 , wherein a weightage of each weighted ratio is based on block size.

6. The data storage device of claim 1 , wherein a weightage of each weighted ratio is based on a configuration of the memory.

7. The data storage device of claim 1 , wherein a weightage of each weighted ratio is provided in a configuration file used by the processor.

8. The data storage device of claim 1 , wherein the processor is further configured to determine whether to perform the garbage collection operation in response to a number of free blocks in the memory falling below a free block threshold.

9. The data storage device of claim 8 , wherein the free block threshold is configurable.

10. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

11. The data storage device of claim 1 , wherein the processor is part of a memory controller.

12. In a data storage device comprising a memory, a method comprising:

in response to a number of pages in the memory that have been written to by a host being above a first threshold, moving a page of data from a source block in the memory to a destination block in the memory as part of a garbage collection operation;

in response to the number of pages in the source block that have been written to by the host being above a second threshold, verifying that the page of data from the source block was successfully written to the destination block; and

in response to the number of pages in the source block that have been written to by the host being above a third threshold, updating a logical-to-physical address map to reflect that the page of data was successfully written to the destination block;

wherein the first, second, and third thresholds comprise different weighted ratios of a valid fragment count in the source block to an invalid fragment count in the source block.

13. The method of claim 12 , wherein a number of blocks freed by the garbage collection operation equals a sum of a number of blocks used to store valid data relocated by the garbage collection operation and a number of blocks used to store incoming host data.

14. The method of claim 12 , further comprising:

determining the different weighted ratios by dividing the valid fragment count by a difference between a maximum valid fragment count and the valid fragment count.

15. The method of claim 12 , wherein a weightage of each weighted ratio is based on an incoming write length of host data.

16. The method of claim 12 , wherein a weightage of each weighted ratio is based on block size.

17. The method of claim 12 , wherein a weightage of each weighted ratio is based on a configuration of the memory.

18. The method of claim 12 , further comprising:

determining whether to perform the garbage collection operation in response to a number of free blocks in the memory falling below a free block threshold.

19. A data storage device comprising:

a memory; and

means for:

in response to a number of pages in the memory that have been written to by a host being above a first threshold, moving a page of data from a source block in the memory to a destination block in the memory as part of a garbage collection operation;

in response to the number of pages in the source block that have been written to by the host being above a second threshold, verifying that the page of data from the source block was successfully written to the destination block; and

in response to the number of pages in the source block that have been written to by the host being above a third threshold, updating a logical-to-physical address map to reflect that the page of data was successfully written to the destination block;

wherein the first, second, and third thresholds comprise different weighted ratios of a valid fragment count in the source block to an invalid fragment count in the source block.

20. The method of claim 12 , wherein the method is performed by a processor in the data storage device.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2023
From: CHOUDHARY, ANAMIKA; RAMAMURTHY, RAMKUMAR; RAVIMOHAN, NARENDHIRAN CHINNAANANGUR; SINGLA, LOVISH; C, MEENAKSHI; KUMARESAN, BHAGYASHANKAR MUTHU
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064376/0693 →
Continuity (2)
Provisional Application 63472403 · Jun 12, 2023
Related Publication 20240411688A1 · Dec 12, 2024
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