IP Library Granted Patent US 10,445,251
Granted Patent B2
US 10,445,251 · App. 15/627,135 · Granted Oct 15, 2019

Wear leveling in non-volatile memories

Inventor: Kiran Kumar Gunnam (Milpitas, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/1072G06F7/768G06F12/0246G06F12/0607G06F2212/1044G06F2212/152G06F2212/7201G06F2212/7211
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Quick Facts
Patent No.
US 10,445,251
App. No.
15/627,135
Granted
Oct 15, 2019
Kind
B2
Abstract

Systems and methods for wear leveling in non-volatile memories (NVMs) are illustrated. One such system includes a first non-volatile memory configured to store information from a host, a second non-volatile memory storing a plurality of cumulative control states, each indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of the first non-volatile memory, and a plurality of control states, an access network configured to translate LBAs to PBAs based on the plurality of cumulative control states, a background swap scheduler configured to swap PBAs assigned to LBAs based on the plurality of control states, and a controller configured to sequentially advance through the plurality of cumulative control states and the plurality of control states.

Claims (67)

1. A non-volatile memory system configured for wear leveling, the system comprising:

a first non-volatile memory configured to store information from a host;

a second non-volatile memory storing a plurality of cumulative control states, each indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of the first non-volatile memory, and a plurality of control states;

an access network configured to translate LBAs to PBAs based on the plurality of cumulative control states;

a background swap scheduler configured to swap PBAs assigned to LBAs based on the plurality of control states; and

a controller configured to sequentially advance through the plurality of cumulative control states and the plurality of control states.

2. The system of claim 1 , wherein the second non-volatile memory comprises a read only memory (ROM).

3. The system of claim 1 :

wherein the cumulative control state comprises a first cumulative control state and a second cumulative control state;

wherein the control state comprises a first control state and a second control state; and

wherein the second cumulative control state is a function of the first cumulative control state and the second control state.

4. The system of claim 3 , wherein the second cumulative control state comprises switch settings used to achieve a sort of a permutation of the first cumulative control state where the permutation is generated using the second control state.

5. The system of claim 1 , further comprising:

a mapping state generator configured to change from a first memory map to a second memory map after the background swap scheduler swaps a preselected number of PBAs;

wherein the first memory map and the second memory map each comprises a preselected number of PBAs.

6. The system of claim 1 , wherein the background swap scheduler is configured to swap PBAs after a preselected number of accesses of the first non-volatile memory.

7. The system of claim 6 , wherein preselected number of accesses comprises 100 writes of the first non-volatile memory.

8. The system of claim 1 , wherein the access network is further configured to:

generate a first PBA candidate from a LBA using a first function;

generate a second PBA candidate from the LBA using a second function; and

select either the first PBA candidate or the second PBA candidate for data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

9. The system of claim 8 , wherein at least one of the first function or the second function comprises a function performed by at least one of a multi-stage interconnection network or a block cipher.

10. A method for wear leveling in a non-volatile memory system, the method comprising:

storing information in a first non-volatile memory;

storing a plurality of cumulative control states, each indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of the first non-volatile memory, and a plurality of control states in a second non-volatile memory;

translating LBAs to PBAs based on the plurality of cumulative control states;

swapping PBAs assigned to LBAs based on the plurality of control states; and

advancing sequentially through the plurality of cumulative control states and the plurality of control states.

11. The method of claim 10 , wherein the storing the plurality of cumulative control states and the plurality of control states comprises:

calculating the plurality of cumulative control states and the plurality of control states; and

storing the plurality of cumulative control states and the plurality of control states.

12. The method of claim 10 , wherein the second non-volatile memory comprises a read only memory (ROM).

13. The method of claim 10 :

wherein the cumulative control state comprises a first cumulative control state and a second cumulative control state;

wherein the control state comprises a first control state and a second control state; and

wherein the second cumulative control state is a function of the first cumulative control state and the second control state.

14. The method of claim 13 , wherein the second cumulative control state comprises switch settings used to achieve a sort of a permutation of the first cumulative control state where the permutation is generated using the second control state.

15. The method of claim 10 , further comprising:

changing from a first memory map to a second memory map after swapping a preselected number of PBAs;

wherein the first memory map and the second memory map each comprises a preselected number of PBAs.

16. The method of claim 10 , wherein the swapping PBAs assigned to LBAs based on the control state comprises swapping PBAs after a preselected number of accesses of the first non-volatile memory.

17. The method of claim 16 , wherein preselected number of accesses comprises 100 writes of the first non-volatile memory.

18. The method of claim 10 , further comprising:

generating a first PBA candidate from a LBA using a first function;

generating a second PBA candidate from the LBA using a second function; and

selecting either the first PBA candidate or the second PBA candidate for data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

19. The method of claim 18 , wherein at least one of the first function or the second function comprises a function performed by at least one of a multi-stage interconnection network or a block cipher.

20. A non-volatile memory system configured for wear leveling, the system comprising:

a first non-volatile means for storing information;

a second non-volatile means for storing a plurality of cumulative control states, each indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of the first non-volatile means, and a plurality of control states;

means for translating LBAs to PBAs based on the plurality of cumulative control states;

means for swapping PBAs assigned to LBAs based on the plurality of control states; and

means for advancing sequentially through the plurality of cumulative control states and the plurality of control states.

21. The system of claim 20 :

wherein the cumulative control state comprises a first cumulative control state and a second cumulative control state;

wherein the control state comprises a first control state and a second control state; and

wherein the second cumulative control state is a function of the first cumulative control state and the second control state.

22. The system of claim 21 , wherein the second cumulative control state comprises switch settings used to achieve a sort of a permutation of the first cumulative control state where the permutation is generated using the second control state.

23. The system of claim 20 , further comprising:

means for changing from a first memory map to a second memory map after swapping a preselected number of PBAs;

wherein the first memory map and the second memory map each comprises a preselected number of PBAs.

24. The system of claim 20 , wherein the means for swapping PBAs assigned to LBAs based on the control state comprises means for swapping PBAs after a preselected number of accesses of the first non-volatile means.

25. The system of claim 24 , wherein the preselected number of accesses comprises 100 writes of the first non-volatile means.

26. The system of claim 20 , further comprising:

means for generating a first PBA candidate from a LBA using a first function;

means for generating a second PBA candidate from the LBA using a second function; and

means for selecting either the first PBA candidate or the second PBA candidate for data access based on information related to a background swap of data stored at the first PBA candidate and a background swap of data stored at the second PBA candidate.

Assignments (10)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 19, 2017
From: GUNNAM, KIRAN KUMAR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 042751/0313 →