Multi-phased programming with balanced gray coding
Disclosed are systems and methods for providing multi-phased programming with balanced Gray coding. A method includes programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode. The method also includes retaining, in a cache, at least a subset of the data. The method also includes regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data. The method also includes programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode. The mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode, and a width of each state distribution in the first-level cell mode may be narrowed.
1. A data storage device, comprising:
a flash memory comprising memory cells;
a cache; and
a controller configured to:
program, in a first phase, a first portion of data into the memory cells in a first-level cell mode;
retain, in the cache, at least a subset of the data;
regenerate the data from at least the cache, wherein the regenerated data includes a second portion of the data; and
program, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode,
wherein the mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode,
wherein the mapping configures a width of each state distribution in the first-level cell mode to be less than a combined width of corresponding state distributions in the second-level cell mode, and
wherein the mapping is configured to provide a balanced Gray code in the second-level cell mode, wherein a difference between transition counts of every two adjacent pages of memory pages in the second-level cell mode does not exceed a predetermined transition count difference, and a sum of the transition counts for all of the memory pages does not exceed a maximum number of programming levels in the second-level cell mode.
2. The data storage device of claim 1 , wherein the controller is configured to retain, in the cache, no more than the first portion of the data in single-level memory cells (SLC).
3. The data storage device of claim 1 , wherein the controller is configured to regenerate the data by reading the first portion of the data from the programmed memory cells and combining the first portion of the data with the at least the subset of the data from the cache.
4. The data storage device of claim 1 , wherein the controller is configured to retain, in the cache, the second portion of the data.
5. The data storage device of claim 4 , wherein the controller is configured to retain, in the cache, the first portion of the data.
6. The data storage device of claim 1 , wherein the controller is configured to program the first phase and the second phase in a staggered progression across wordlines of the memory cells.
7. The data storage device of claim 1 , wherein the mapping is configured so that the width of each state distribution in the first-level cell mode is approximately half of the combined width of the corresponding state distributions in the second-level cell mode.
8. The data storage device of claim 1 , wherein the controller is configured to retain, in the cache, up to a predetermined number of memory pages.
9. The data storage device of claim 1 , wherein the cache is separate and distinct from the flash memory.
10. The data storage device of claim 3 , wherein the cache comprises volatile random access memory, and wherein the flash memory comprises non-volatile memory.
11. A method implemented using one or more controllers for one or more storage devices, the method comprising:
programming, in a first phase, a first portion of data into memory cells of a flash memory in a first-level cell mode;
retaining, in a cache comprising single-level cells (SLC), at least a subset of the data;
regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data; and
programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode,
wherein the mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode,
wherein the mapping provides a width of each state distribution in the first-level cell mode that is less than a combined width of corresponding state distributions in the second-level cell mode, and
wherein the mapping is configured to provide a balanced Gray code in the second-level cell mode, wherein a difference between transition counts of every two adjacent pages of memory pages in the second-level cell mode does not exceed a predetermined transition count difference, and a sum of the transition counts for all of the memory pages does not exceed a maximum number of programming levels in the second-level cell mode.
12. The method of claim 11 , wherein regenerating the data comprises reading the first portion of the data from the programmed memory cells and combining the first portion of the data with the at least the subset of the data from the cache.
13. The method of claim 11 , wherein the at least the subset of the data includes the second portion of the data.
14. The method of claim 13 , wherein the at least the subset of the data includes the first portion of the data.
15. The method of claim 11 , wherein programming in the first phase and programming in the second phase executes in a staggered progression across wordlines of the memory cells.
16. The method of claim 11 , wherein the mapping is configured so that the width of each state distribution in the first-level cell mode is approximately half of the combined width of the corresponding state distributions in the second-level cell mode.
17. A system, comprising:
means for programming, in a first phase, a first portion of data into memory cells of a flash memory in a multi-level cell (MLC) mode;
means for retaining, in a cache comprising single-level cells (SLC), at least a subset of the data;
means for regenerating the data from at least the cache, wherein the regenerated data includes a second portion of the data; and
means for programming, in a second phase, the regenerated data in a quad-level cell (QLC) mode based on a mapping from the MLC mode to the QLC mode,
wherein the mapping maps each state distribution in the MLC mode to at least two non-adjacent state distributions in the QLC mode, and
wherein the mapping is configured so that a width of each state distribution in the MLC mode is less than a combined width of corresponding state distributions in the QLC mode, and wherein the mapping is configured to provide a balanced Gray code in the MLC mode and the QLC mode.
18. The system of claim 17 , wherein the mapping is configured so that the width of each state distribution in the MLC mode is approximately 50% to 75% of the combined width of the corresponding state distributions in the QLC mode.