System and method for processing non-contiguous submission and completion queues
Systems and methods for processing non-contiguous submission and completion queues are disclosed. Non-Volatile Memory Express (NVMe) implements a paired submission queue and completion queue mechanism, with host software on a host device placing commands into the submission queue. The submission and completion queues may be contiguous or non-contiguous in host device memory. Non-contiguous queues may be defined by a link to a list on the host device that lists the non-contiguous sections in memory. In practice, the memory device stores the list in one type of memory (such as a dynamic random access memory (DRAM) cache) and the link in a different type of memory (such as always-on memory or non-volatile memory). In this way, the link may be accessed in various modes (such as low power mode) in order to recreate the list in DRAM. At least a part of the list of non-contiguous sections may be restored in response to the memory device exiting low power mode, or in response to determining that part or all of the list of noncontiguous sections is corrupted. The list of non-contiguous sections may comprise a list of physical region pages.
1. A method comprising:
storing, in a first type of memory in a memory device, a link to a list of non-contiguous sections in host memory that defines a non-contiguous queue;
storing part or all of the list of non-contiguous sections in a second type of memory in the memory device, the first type of memory maintaining data therein during at least a part of operation of the memory device in which data is not maintained in the second type of memory;
determining to re-store at least a part of the list of non-contiguous sections; and
in response to determining to re-store the at least a part of the list of non-contiguous sections, re-storing the at least a part of the list of non-contiguous sections by:
accessing the link stored in the first type of memory in the memory device;
using the link to access in the host memory at least a part of the list of non-contiguous sections; and
re-storing the at least a part of the list of non-contiguous sections in the second type of memory.
2. The method of claim 1 , wherein the first type of memory comprises always-on memory.
3. The method of claim 2 , wherein:
the first type of memory maintains the data therein during a low power mode of the memory device; and
the second type of memory does not maintain the data therein during the low power mode of the memory device.
4. The method of claim 1 , wherein:
the first type of memory comprises a first type of cache; and
the second type of memory comprises a second type of cache.
5. The method of claim 1 , wherein the list of non-contiguous sections comprises a list of physical region pages.
6. The method of claim 1 , wherein determining to re-store at least a part of the list of non-contiguous sections is performed in response to the memory device exiting low power mode.
7. The method of claim 1 , wherein determining to re-store at least a part of the list of non-contiguous sections is performed in response to determining that the part or all of the list of non-contiguous sections stored in the second type of memory is corrupted.
8. The method of claim 1 , wherein:
the memory device determines a section of the list of non-contiguous sections stored in the second type of memory that is corrupted; and
re-storing the at least a part of the list of non-contiguous sections comprises re-storing the section of the list of non-contiguous sections that is corrupted.
9. The method of claim 1 , wherein:
storing part or all of the list of non-contiguous sections in the second type of memory comprises storing all of the list of non-contiguous sections in the second type of memory; and
re-storing the at least a part of the list of non-contiguous sections in the second type of memory comprises re-storing all of the list of non-contiguous sections in the second type of memory.
10. The method of claim 1 , wherein the non-contiguous queue is a non-contiguous submission queue.
11. The method of claim 1 , wherein:
the first type of memory comprises non-volatile memory; and
the second type of memory comprises cache.
12. A memory device comprising:
memory comprising a first type of memory and a second type of memory, the first type of memory maintaining data therein during a mode of the memory device and the second type of memory not maintaining data therein during the mode of the memory device; and
a controller in communication with the memory, the controller configured to:
store a link in the first type of memory, the link comprising an address in a host device to a list of non-contiguous sections for a queue;
store part or all of the list of non-contiguous sections in the second type of memory;
determine to enter the mode; and
in response to determining to exit the mode:
use the link stored in the first type of memory to access at least a part of the list of non-contiguous sections for the queue in the host device; and
store the at least a part of the list of non-contiguous sections for the queue in the second type of memory.
13. The memory device of claim 12 , wherein:
the first type of memory comprises always-on memory; and
the second type of memory comprises dynamic random access memory (DRAM).
14. The memory device of claim 13 , wherein the controller is further configured to store all of the list of non-contiguous sections in the DRAM.
15. The memory device of claim 12 , wherein:
the first type of memory comprises non-volatile memory; and
the second type of memory comprises cache memory.
16. The memory device of claim 12 , wherein the mode comprises a low power mode.
17. The memory device of claim 16 , wherein the controller is further configured to access the link in always-on memory to store the list of non-contiguous sections for the queue in dynamic random access memory (DRAM) responsive to the controller determining to exit the low power mode.
18. The memory device of claim 17 , wherein the queue is a submission queue.