Optimal programming levels for LDPC
View Patent ↗The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.
1. A method for reducing a sector error rate in a flash memory device, the method comprising:
identifying a first program verify voltage level having a first value;
selecting an adjustment value for the first program verify voltage level; and
programming the adjustment value to the first program verify voltage level to replace the first value and to shift a first programming distribution associated with the first program verify voltage level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, and
wherein the shift in the first programming distribution is associated with an increase in a bit error rate.
2. The method of claim 1 , further comprising:
identifying a second program verify voltage level having a second value;
selecting a second adjustment value for the second program verify voltage level; and
programming the second adjustment value to the second program verify voltage level to replace the second value and to shift the second programming distribution, wherein the shift in the second programming distribution is associated with an increase in the bit error rate.
3. The method of claim 2 , wherein selecting an adjustment value for the first program verify voltage level and selecting an adjustment value for the second program verify voltage level is performed such that a MSB error rate and a LSB error rate of the flash memory device are equal.
4. The method of claim 2 , wherein selecting an adjustment value for the first program verify voltage level and selecting an adjustment value for the second program verify voltage level further comprises:
determining a first voltage shift amount corresponding with the first programming distribution; and
determining a second voltage shift amount corresponding with the second programming distribution, wherein the second voltage shift amount is different from the first voltage shift amount.
5. The method of claim 1 , wherein the decrease in the sector error rate corresponds with a decrease in a LSB error rate.
6. The method of claim 1 , wherein selecting an adjustment value for the first program verify voltage level is performed based on a number of erase/programming cycles of the flash memory device.
7. The method of claim 1 , wherein selecting an adjustment value for the first program verify voltage level is performed based on a bit error rate of the flash memory device.
8. A flash storage device configured to adjust one or more program verify voltage levels, for reducing a sector error rate, the flash storage device comprising:
a flash memory array;
an error correction module coupled to the flash memory array; and
a controller coupled to the error correction module and the flash memory array, wherein the controller is configured to perform operations comprising:
identifying a first program verify voltage level having a first value;
selecting an adjustment value for the first program verify voltage level; and
programming the adjustment value to the first program verify voltage level to replace the first value and to shift a first programming distribution associated with the first program verify voltage level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, and
wherein the shift in the first programming distribution is associated with an increase in a bit error rate.
9. The flash storage device of claim 8 , further comprising:
identifying a second program verify voltage level having a second value;
selecting a second adjustment value for the second program verify voltage level; and
programming the second adjustment value to the second program verify voltage level to replace the second value to shift the second programming distribution, wherein the shift in the second programming distribution is associated with an increase in the bit error rate.
10. The flash storage device of claim 9 , wherein selecting an adjustment value for the first program verify voltage level and selecting an adjustment value for the second program verify voltage level is performed such that a MSB error rate and a LSB error rate of the flash memory device are equal.
11. The flash storage device of claim 9 , wherein selecting an adjustment value for the first program verify voltage level and selecting an adjustment value for the second program verify voltage level further comprises:
determining a first voltage shift amount corresponding with the first programming distribution; and
determining a second voltage shift amount corresponding with the second programming distribution, wherein the second voltage shift amount is different from the first voltage shift amount.
12. The flash storage device of claim 8 , wherein the decrease in the sector error rate corresponds with a decrease in a LSB error rate.
13. The flash storage device of claim 8 , wherein selecting an adjustment value for the first program verify voltage level is performed based on a number of erase/programming cycles of the flash memory device.
14. The flash storage device of claim 8 , wherein selecting an adjustment value for the first program verify voltage level is performed based on a bit error rate of the flash memory device.
15. A non-transitory computer-readable medium comprising instructions stored thereon, which when executed by a processor, cause the processor to perform operations comprising:
identifying a first program verify voltage level having a first value;
selecting an adjustment value for the first program verify voltage level; and
programming the adjustment value to the first program verify voltage level to replace the first value and to shift a first programming distribution associated with the first program verify voltage level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, and
wherein the shift in the first programming distribution is associated with an increase in a bit error rate.
16. The non-transitory computer-readable medium of claim 15 , further comprising:
identifying a second program verify voltage level having a second value;
selecting a second adjustment value for the second program verify voltage level; and
programming the second adjustment value to the second program verify voltage level to replace the second value and to shift the second programming distribution, wherein the shift in the second programming distribution is associated with an increase in the bit error rate.
17. The non-transitory computer-readable medium of claim 16 , wherein selecting an adjustment value for the first program verify voltage level and the second program verify voltage level is performed such that a MSB error rate and a LSB error rate of the flash memory device are equal.
18. The non-transitory computer-readable medium of claim 16 , wherein selecting the adjustment value for the first program verify voltage level and the second program verify voltage level further comprises:
determining a first voltage shift amount corresponding with the first programming distribution; and
determining a second voltage shift amount corresponding with the second programming distribution, wherein the second voltage shift amount is different from the first voltage shift amount.
19. The non-transitory computer-readable medium of claim 15 , wherein the decrease in the sector error rate corresponds with a decrease in a LSB error rate.
20. The non-transitory computer-readable medium of claim 15 , wherein selecting an adjustment value for the first program verify voltage level is performed based on a number of erase/programming cycles of the flash memory device.
21. The non-transitory computer-readable medium of claim 15 , wherein selecting an adjustment value for the first program verify voltage level is performed based on a bit error rate of the flash memory device.
22. A method for reducing a sector error rate in a flash memory device, the method comprising:
identifying a plurality of program verify voltage levels set in the flash memory device, wherein each of the program verify voltage levels is associated with one or more programming levels of the flash memory device;
adjusting a first program verify voltage level of the plurality of program verify voltage levels in the flash memory device to shift a first programming distribution, wherein adjusting the first program verify voltage level is associated with a decrease in a first bit error rate; and
adjusting a second program verify voltage level of the plurality of program verify voltage levels in the flash memory device to shift a second programming distribution, wherein adjusting the second program verify voltage level is associated with an increase in a second bit error rate, and
wherein adjusting the first program verify voltage level and adjusting the second program verify voltage level are associated with an overall decrease in a bit error rate for the flash memory device.
23. The method of claim 22 , wherein adjusting the first program verify voltage level and adjusting the second program verify voltage level are associated with a decrease in a sector error rate for the flash memory device.