Implementing magnetic memory pillar design
View Patent ↗A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M 1 , and a second conductor M 2 , the second conductor M 1 surrounded by the first conductor M 1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M 1 , M 2 is formed of a magnetic material, and the conductor M 2 is more conductive than conductor M 1 . An oxide barrier extends between the first conductor M 1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.
1. A magnetic memory pillar cell comprising:
a first conductor M 1 ,
a second conductor M 2 ;
said second conductor M 2 surrounded by said first conductor M 1 ; said second conductor M 2 coated with a non-magnetic spacer layer, and said first conductor M 1 formed over said second conductor M 2 ;
said first conductor M 1 and said second conductor M 2 being unpatterned;
said first conductor M 1 being formed of a magnetic material said first conductor M 1 and said second conductor M 2 having different electrical conductivity, and said second conductor M 2 being more electrically conductive than said conductor M 1 ; and
an oxide barrier extending between said first conductor M 1 and a programmable input to said magnetic memory pillar cell; said oxide barrier being unpatterned, and current flowing though said oxide barrier and said first conductor M 1 for programming the magnetic memory pillar cell.
2. The magnetic memory pillar cell as recited in claim 1 wherein said second conductor M 2 is formed of a magnetic material.
3. The magnetic memory pillar cell as recited in claim 1 wherein said second conductor M 2 is formed of a non-magnetic material.
4. The magnetic memory pillar cell as recited in claim 1 wherein said second conductor M 2 is formed of a magnetic material and has a fixed magnetization direction, and said first conductor M 1 is programmable in one of a parallel or anti-parallel magnetization state.
5. The magnetic memory pillar cell as recited in claim 1 wherein said magnetic memory pillar cell is programmed in at least one of its magnetization states by a selected one of a spin-biased steered current and a spin-biased tunneling current.
6. The magnetic memory pillar cell as recited in claim 1 includes an array of a plurality of said magnetic memory pillar cells and said array includes a respective programmable input for each of said plurality of magnetic memory pillar cells.
7. The magnetic memory pillar cell as recited in claim 6 includes a respective one of said plurality of programmable inputs is activated to program a targeted one of said magnetic memory pillar cells; and wherein programmed states of other non-targeted magnetic memory pillar cells remain unchanged.
8. The magnetic memory pillar cell as recited in claim 6 wherein other non-targeted magnetic memory pillar cells are placed in a state and remain unchanged while a programming current is used to program a targeted magnetic memory pillar cell.
9. The magnetic memory pillar cell as recited in claim 6 wherein other non-targeted magnetic memory pillar cells are placed in a state and remain unchanged while a readout current is used to read content of a targeted magnetic memory pillar cell.
10. The magnetic memory pillar cell as recited in claim 1 wherein a magnetization state of said magnetic memory pillar cell is sensed in a readout operation with a selected one of a steered current flowing toward a programmable cell area and a steered current flowing from said magnetic memory pillar cell through said oxide barrier.
11. The magnetic memory pillar cell as recited in claim 1 wherein each of said first conductor and said second conductor is formed of a magnetic material.
12. The magnetic memory pillar cell as recited in claim 2 wherein said second conductor is formed of a non-magnetic material.
13. The magnetic memory pillar cell as recited in claim 1 wherein said second conductor is formed of a magnetic material and has a fixed magnetization direction, and said first conductor is programmable in one of a parallel or anti-parallel magnetization state.
14. A method for implementing a magnetic memory pillar cell comprising:
providing a first conductor M 1 ,
providing a second conductor M 2 with said second conductor M 2 surrounded by said first conductor M 1 by coating said second conductor M 2 with a non-magnetic spacer layer, and forming said first conductor M 1 over said second conductor M 2 , said first conductor M 1 and said second conductor M 2 being unpatterned;
forming said first conductor M 1 of a magnetic material with said first conductor M 1 and said second conductor M 2 having different electrical conductivity, and said second conductor M 2 being more electrically conductive than said conductor M 1 ; and
providing an oxide barrier extending between said first conductor M 1 and a programmable input to said magnetic memory pillar cell; said oxide barrier being unpatterned; and programming the magnetic memory pillar cell with current flowing though said oxide barrier and said first conductor M 1 .
15. The method as recited in claim 14 includes providing an array of a plurality of said magnetic memory pillar cells and providing a respective programmable input for each of said magnetic memory pillar cells.
16. The method as recited in claim 15 includes activating a respective one of said plurality of programmable inputs to program a targeted one of said magnetic memory pillar cells; and wherein programmed states of other non-targeted magnetic memory pillar cells remain unchanged.
17. The method as recited in claim 15 includes programming a targeted one of said magnetic memory pillar cells using a selected one of a spin-biased steered current and spin-biased tunneling current; and wherein programmed states of other non-targeted magnetic memory pillar cells remain unchanged.
18. The method as recited in claim 15 includes using a readout current to read content of a targeted magnetic memory pillar cell wherein other non-targeted magnetic memory pillar cells are placed in a state and remain unchanged.
19. The method as recited in claim 18 includes sensing a magnetization state of said magnetic memory pillar cell in a readout operation with a steered current.
20. A magnetic memory pillar cell comprising:
conductor means for forming said magnetic memory pillar cell;
said conductor means including a first conductor and a second conductor; said first conductor and said second conductor having different electrical conductivity, and said second conductor being more electrically conductive than said conductor;
said second conductor surrounded by said first conductor; said second conductor coated with a non-magnetic spacer layer, and said first conductor formed over said second conductor; and
an oxide barrier extending between said first conductor and a programmable input to said magnetic memory pillar cell; said oxide barrier being unpatterned, and current flowing though said oxide barrier and said first conductor for programming the magnetic memory pillar cell.