IP Library Granted Patent US 11,456,272
Granted Patent B2
US 11,456,272 · App. 17/171,576 · Granted Sep 27, 2022

Straight wirebonding of silicon dies

Inventors: Kirubakaran Periyannan (Santa Clara, CA); Daniel Linnen (Naperville, IL); Jayavel Pachamuthu (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
H01L24/48H01L24/05H01L24/32H01L24/45H01L24/49H01L24/73H01L24/85H01L24/92H01L25/0657H01L2224/04042H01L2224/0556H01L2224/05573H01L2224/32145H01L2224/4501H01L2224/45147H01L2224/45611H01L2224/4899H01L2224/48108H01L2224/48145H01L2224/48147H01L2224/48221H01L2224/48496H01L2224/48499H01L2224/49175H01L2224/73265H01L2224/85007H01L2224/85815H01L2224/92247H01L2225/0651H01L2225/06506H01L2225/06551H01L2924/0105H01L2924/01029H01L2924/01046H01L2924/01047H01L2924/01049H01L2924/01077H01L2924/01079H01L2924/01082H01L2924/10253H01L2924/14511
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Quick Facts
Patent No.
US 11,456,272
App. No.
17/171,576
Granted
Sep 27, 2022
Kind
B2
Abstract

A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.

Claims (35)

1. An apparatus comprising:

a substrate;

two or more silicon dice, wherein a first die is disposed on the substrate and a second die is stacked on the first die, and the dice comprising:

an upper planar surface parallel to the substrate;

a lower planar surface parallel to the upper planar surface and spaced at a first distance from the upper planar surface;

at least a first edge portion disposed between, and perpendicular to, the upper planar surface and the lower planar surface; and

at least a first set of connection pads disposed on the at least first edge portion and wherein the first set of connection pads are in vertical alignment with each other;

a conductive element configured to be coupled to the first set of connection pads; and

a plurality of solder blocks coupled to the conductive element and spaced at an interval associated with a distance between the connection pads of the first set of connection pads.

2. The apparatus of claim 1 , wherein the solder blocks are configured to be heated such that the solder blocks reflow and create a soldered connection between the conductive element and the first set of connection pads.

3. The apparatus of claim 1 , wherein the solder blocks comprise a first groove having a width measuring approximately the same as the first distance and configured to accept the edge of the silicon dice within the first groove.

4. The apparatus of claim 3 , wherein the width of the first groove is 10% wider than the width of the first edge portion.

5. The apparatus of claim 4 , wherein the width of the first edge portion is 25 microns.

6. The apparatus of claim 1 , wherein the conductive element is electrically connected to the substrate.

7. The apparatus of claim 6 , wherein the substrate includes a channel and the conductive element is electrically connected to the substrate within the channel.

8. The apparatus of claim 1 , further comprising means for attaching the first die to the second die.

9. The apparatus of claim 1 , further comprising a die attach film disposed between and physically connecting the first and second dice.

10. The apparatus of claim 1 , further comprising means for spacing the first die from the second die.

11. The apparatus of claim 1 , wherein the conductive element comprises a tin plated copper wire.

12. The apparatus of claim 1 , wherein a first subset of the two or more silicon dice have the first set of connection pads on the first edge, and a second subset of the two or more of silicon dice have a second set of connection pads on a second edge, wherein the second edge is different than the first edge.

13. The apparatus of claim 12 , wherein the two or more silicon dice are arranged such that each of the first subset of the two or more silicon dice are alternated with the second subset of the two or more silicon dice.

14. The apparatus of claim 1 , wherein at least one of the conductive element and the connection pads are coated in a flux material.

15. The apparatus of claim 1 , wherein the conductive solder is comprised of at least one selected from the group consisting of gold, indium, iridium, tin-plated copper, and palladium.

16. A method comprising:

stacking a plurality of silicon dice such that one or more edges of the plurality of silicon dice are in vertical alignment, wherein the one or more edges include a plurality of connection pads;

positioning a substantially linear conductor on a substantially perpendicular axis to the one or more edges, wherein the linear conductor is in contact with one or more of the plurality of connection pads;

applying a conductive solder to the one or more connection pads and one or more portions of the linear conductor in contact with the one or more connection pads; and

applying heat to reflow the solder, to cause the solder to physically and electrically couple the one or more portions of the linear conductor to the one or more connection pads in contact therewith.

17. The method of claim 16 , further comprising coating the linear conductor with a layer of flux.

18. The method of claim 16 , wherein the conductive solder is applied by applying heated liquid solder to the one or more connection pads and the one or more portions of the linear conductor in contact with the one or more connection pads.

19. A method comprising:

stacking a plurality of silicon dice such that one or more edges of the plurality of silicon dice are in vertical alignment, wherein the one or more edges include a plurality of connection pads;

positioning a connecting wire on a substantially perpendicular axis to the one or more edges, wherein the connecting wire comprises a plurality of solder blocks spaced at an interval associated with a distance between a first set of aligned connection pads on the plurality of silicon dice, and wherein the connecting wire is positioned such that the plurality of solder blocks are in contact with the first set of aligned connection pads;

applying heat to reflow the solder blocks to cause the solder blocks to physically couple the connecting wire to the aligned connection pads.

20. The method of claim 19 , wherein a flame jet heating process is used to reflow the solder blocks.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2021
From: PERIYANNAN, KIRUBAKARAN; LINNEN, DANIEL; PACHAMUTHU, JAYAVEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055201/0149 →
Continuity (2)
Provisional Application 63077069 · Sep 11, 2020
Related Publication 20220084979A1 · Mar 17, 2022