Low latency parity for a memory device
Apparatuses, systems, and methods for low latency parity for a memory device include a controller configured to accumulate, in a memory buffer, combined parity data for a plurality of regions of memory of a memory device in response to write operations for the plurality of regions of memory. The controller is configured to perform a recovery operation for a region of memory in response to determining that a latency setting for the region satisfies a latency threshold. The controller is configured to service a read request for data from the region based on a recovery operation to satisfy the latency setting.
1. An apparatus comprising:
a controller for a memory device, the controller configured to:
accumulate, in a memory buffer, combined parity data for a plurality of regions of memory of the memory device in response to write operations for the plurality of regions of memory;
perform a recovery operation for a region of the plurality of regions in response to determining that a latency setting for the region satisfies a latency threshold, the recovery operation performed proactively, prior to receiving a read request, wherein the latency setting comprises a disabled extended error recovery setting; and
service the read request for data from the region based on the recovery operation to satisfy the latency setting.
2. The apparatus of claim 1 , wherein the recovery operation for the region comprises a reverse parity operation to recover the data from the region.
3. The apparatus of claim 2 , wherein the recovery operation for the region further comprises:
removing invalid data of at least the region of the plurality of regions from the combined parity data; and
determining new parity data for remaining valid data from at least the region of the plurality of regions, the read request being serviced using the new parity data.
4. The apparatus of claim 1 , wherein accumulating the combined parity data comprises one or more XOR operations and the recovery operation comprises one or more reverse XOR operations.
5. The apparatus of claim 1 , wherein the latency setting comprises a read recovery level setting.
6. The apparatus of claim 5 , wherein the read recovery level setting comprises a fast fail level providing a minimum level of recovery.
7. The apparatus of claim 6 , wherein the fast fail level comprises a Non-Volatile Memory Express (NVMe) read recovery level of fifteen, and higher levels provide less recovery than preceding lower levels for the read recovery level setting.
8. The apparatus of claim 1 , wherein the controller is configured to automatically determine the latency setting for the region based on a type of data stored by the region.
9. The apparatus of claim 1 , wherein the controller is configured to receive the latency setting for the region from a host computing device.
10. The apparatus of claim 1 , wherein the controller is configured to perform recovery operations for different regions of the memory device at different frequencies based on different latency settings for the different regions.
11. A method comprising:
accumulating, in a memory buffer, combined parity data for a plurality of blocks of memory of a memory device in response to write operations for the plurality of blocks of memory;
performing a recovery operation for a block of the plurality of blocks in response to determining that a latency setting for the block satisfies a latency threshold, the recovery operation performed proactively, prior to receiving a read request, wherein the latency setting comprises a disabled extended error recovery setting; and
servicing the read request for data from the block based on the recovery operation to satisfy the latency setting.
12. The method of claim 11 , wherein the recovery operation for the block further comprises:
removing invalid data of at least the block of the plurality of blocks from the combined parity data; and
determining new parity data for remaining valid data from at least the block of the plurality of blocks, the read request being serviced using the new parity data.
13. The method of claim 11 , further comprising automatically determining the latency setting for the block based on a type of data stored by the block.
14. The method of claim 11 , further comprising receiving the latency setting for the block from a host computing device.
15. The method of claim 11 , further comprising performing recovery operations for different blocks of the memory device at different frequencies based on different latency settings for the different blocks.
16. An apparatus comprising:
means for accumulating, in a memory buffer, combined parity data for a plurality of blocks of non-volatile memory of a non-volatile memory device in response to write operations for the plurality of blocks of non-volatile memory;
means for performing a recovery operation for a block of the plurality of blocks in response to determining that a latency setting for the block satisfies a latency threshold, the recovery operation performed proactively, prior to receiving a read request, wherein the latency setting comprises a disabled extended error recovery setting; and
means for servicing the read request for data from the block based on the recovery operation to satisfy the latency setting.
17. The apparatus of claim 16 further comprising:
means for removing invalid data of at least the block of the plurality of blocks from the combined parity data; and
means for determining new parity data for remaining valid data from at least the block of the plurality of blocks, the read request being serviced using the new parity data.