IP Library Granted Patent US 10,831,656
Granted Patent B2
US 10,831,656 · App. 16/157,076 · Granted Nov 10, 2020

System and method to improve input output command latency by dynamic size logical to physical caching

Inventors: Jameer Babasaheb Mulani (Bangalore, IN); Anindya Rai (Bangalore, IN); Devanathan Balasundaram (Bangalore, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, Inc.
G06F12/0802G06F13/1668G06F2212/7201G06F2213/0064
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Quick Facts
Patent No.
US 10,831,656
App. No.
16/157,076
Filed
Oct 10, 2018
Granted
Nov 10, 2020
Kind
B2
Examiner
CHOE, YONG J
Art Unit
2135
USPC
711/118
Abstract

A method and apparatus are provided to divide a logical to physical table into multiple parts, one part in a first fast memory and a second part in a second non-volatile memory, wherein an algorithm may be used in the division.

Claims (55)

1. A method for operating an apparatus, comprising:

obtaining a logical to physical table for the apparatus, the logical to physical mapping logical entities to physical entities;

analyzing data in the logical to physical table;

choosing a parameter to determine a first portion and a second portion of a dynamic logical to physical table;

sorting the logical to physical table according to the chosen parameter; and

apportioning a size of the first portion and the second portion of the dynamic logical to physical table based on the parameter.

2. The method according to claim 1 , wherein the first portion of the logical to physical table is placed in a fast memory.

3. The method according to claim 2 , wherein the fast memory is a volatile memory.

4. The method according to claim 1 , wherein the second portion of the logical to physical table is placed in a slow memory.

5. The method according to claim 4 , wherein the slow memory is a DDR memory.

6. The method according to claim 4 , wherein the slow memory is a NAND flash memory.

7. The method according to claim 1 , wherein the parameter is a namespace.

8. The method according to claim 1 , further comprising:

saving the first portion to a fast memory and saving the second portion to a slow memory.

9. An arrangement for augmenting a logical to physical table, comprising:

means for analyzing data in the logical to physical table;

means for choosing a parameter to determine a first portion and a second portion of a dynamic logical to physical table;

means for sorting the logical to physical table according to the chosen parameter; and

means for apportioning a size of the first portion and the second portion of the dynamic logical to physical table based on the parameter.

10. The arrangement according to claim 9 , further comprising:

means for saving the first portion to a fast memory and saving the second portion to a slow memory.

11. A method for operating an apparatus, comprising:

obtaining a logical to physical table;

choosing a parameter to determine a first portion and a second portion of the logical to physical table;

apportioning the first portion and the second portion of the logical to physical table based upon the chosen parameter;

performing operations based upon the logical to physical table;

determining if the performed operations with the logical to physical table include the second portion of the logical to physical table; and

augmenting the logical to physical table, wherein data in the second portion of the logical to physical table used in operations are placed in the first portion of the logical to physical table.

12. The method according to claim 11 , further comprising:

saving the logical to physical table after the apportioning the first portion and the second portion of the logical to physical table based upon the chosen parameter.

13. The method according to claim 11 , further comprising:

saving the logical to physical table after the augmenting the logical to physical table, wherein data in the second portion of the logical to physical table used in operations are placed in the first portion of the logical to physical table.

14. The method according to claim 11 , wherein the first portion of the logical to physical table is placed in a fast memory.

15. The method according to claim 14 , wherein the fast memory is a volatile memory.

16. The method according to claim 11 , wherein the second portion of the logical to physical table is placed in a slow memory.

17. The method according to claim 16 , wherein the slow memory is a DDR memory.

18. The method according to claim 16 , wherein the slow memory is a NAND flash memory.

19. The method according to claim 11 , wherein the parameter is a namespace.

20. The method according to claim 11 , wherein the parameter is a type and amount of input output workload for a namespace.

21. The method according to claim 20 , wherein an algorithm is used to determine an amount of first portion capacity and a second portion capacity.

22. An arrangement for augmenting a logical to physical table, comprising:

means for choosing a parameter to determine a first portion and a second portion of the logical to physical table;

means for apportioning the first portion and the second portion of the logical to physical table based upon the chosen parameter;

means for performing operations based upon the logical to physical table;

means for determining if the performed operations with the logical to physical table include the second portion of the logical to physical table; and

means for augmenting the logical to physical table, wherein data in the second portion of the logical to physical table used in operations are placed in the first portion of the logical to physical table.

23. The arrangement according to claim 22 , further comprising:

means for saving the logical to physical table after the augmenting the logical to physical table, wherein data in the second portion of the logical to physical table used in operations are placed in the first portion of the logical to physical table.

24. A method for operating a solid state drive, comprising:

obtaining a logical to physical table, the logical to physical table tabulating locations of data stored on the solid state drive;

choosing a parameter to divide the logical to physical table into at least a first portion and a second portion;

dividing the logical to physical table into the first portion and the second portion based upon the chosen parameter; and

storing the first portion of the logical to physical table in a first memory and the second portion of the logical to physical table in a second memory.

25. The method according to claim 24 , wherein the first memory is a volatile memory and the second memory is a non-volatile memory.

26. The method according to claim 24 , wherein the parameter is used by an algorithm for the dividing the logical to physical table.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2018
From: MULANI, JAMEER BABASAHEB; RAI, ANINDYA; BALASUNDARAM, DEVANATHAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 047131/0829 →