Detecting last page written in multi-plane non-volatile memory
A memory device includes logic to detect the last page written in multi-plane non-volatile memory. The device includes a memory array, and a storage controller. The memory array includes multiple planes and multiple word lines operable on the memory array. The storage controller is configured to divide the word lines into contiguous sub-ranges and assign a subset of the word lines to boundaries of the sub-ranges. Each word line of the subset of word lines is assigned to a page in a different one of the memory planes. The controller operates the subset of word lines to sense a page programmed or erased state from each of the memory planes in parallel.
1. A device, comprising:
a memory array including a plurality of planes;
a plurality of word lines operable on the memory array; and
a storage controller configured to:
divide the word lines into R>2 contiguous sub-ranges, wherein R is a number of the contiguous sub-ranges;
assign a subset of the word lines to boundaries of the sub-ranges, wherein each word line of the subset of word lines is assigned to a page in a different one of P=R−1 memory planes, wherein P is a number of planes, and wherein P is greater than 1; and
operate the subset of word lines to sense a page programmed or erased state from each of the P memory planes in parallel.
2. The device of claim 1 , wherein a first physical page on a first memory plane and a second physical page on a second memory plane defines a sub-range.
3. The device of claim 1 , the storage controller further configured to:
reduce a total range of the sub-ranges by a factor of P/R to generate a reduced range of word lines; and
divide the reduced range of word lines into R contiguous sub-ranges.
4. The device of claim 1 , the storage controller further configured to switch to performing an alternative search of the plurality of word lines upon detection of a predetermined degenerate condition.
5. The device of claim 1 , the storage controller further configured to execute a sense loop to:
sense each of the subset of word lines for a last erased memory page on the P memory planes in parallel; and
reduce a extent of the sub-ranges by P/R on each iteration of the sense loop.
6. The device of claim 5 , the storage controller further configured to: change at least one of the boundaries of the sub-ranges on each iteration of the sense loop.
7. The device of claim 5 , the storage controller further configured to:
terminate the sense loop when the extent of the sub-ranges satisfies a configured extent.
8. A method, comprising:
dividing a range of memory pages into R>2 contiguous sub-ranges, wherein R is a number of the contiguous sub-ranges;
assigning a set of pages at boundaries of the sub-ranges;
operating a storage controller to sense the set of pages at the boundaries across P=R−1 memory planes in parallel, wherein P is a number of planes, and wherein P is greater than 1; and
reducing the range by a factor of P/R.
9. The method of claim 8 , wherein each of the boundaries of the sub-ranges is assigned to different one of the memory planes.
10. The method of claim 8 , wherein the pages are programmed contiguously in a sequential order.
11. The method of claim 8 , wherein:
the range includes T p pages; and
each of the sub-ranges includes T p /R pages.
12. The method of claim 8 , wherein each of the pages in the set of pages is a physical page of a logical page in a memory meta-block.
13. The method of claim 8 , wherein a first page on a first memory plane and a second page on a second memory plane defines a sub-range.
14. The method of claim 8 , wherein the memory planes are distributed across a plurality of memory die.
15. A memory system, comprising:
a plurality of D memory die, each of the D memory die including a plurality of P memory planes; and
logic configured to:
test in parallel for either a programmed state or an erased state of a memory page on D*P word lines of a range R of word lines, each word line sensing a page from a different one of the memory planes;
reduce the range R by a factor of (D*P)/(D*P+1); and
repeat the test step and the reduce step until R satisfies a configured condition.
16. The memory system of claim 15 , wherein the logic is further configured to:
operate each of the word lines to sense a physical page at a boundary of a configured sub-range of the range.
17. The memory system of claim 15 , wherein pages of each of the memory planes are programmed contiguously in a same sequential order.
18. The memory system of claim 15 , wherein the configured condition is that R is empty.
19. The memory system of claim 15 , wherein pages from the different memory planes form a logical page.
20. The memory system of claim 15 , wherein the pages from the different memory planes form a memory meta-block.