IP Library Granted Patent US 12,360,701
Granted Patent B2
US 12,360,701 · App. 17/885,265 · Granted Jul 15, 2025

Write coalescing via HMB to optimize write performance

Inventors: Shay Benisty (Beer Sheva, IL); Alexander Bazarsky (Holon, IL); Judah Gamliel Hahn (Ofra, IL); Ariel Navon (Revava, IL)
Assignee: Sandisk Technologies, Inc.
G06F3/0659G06F3/0604G06F3/0656G06F3/0673
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Quick Facts
Patent No.
US 12,360,701
App. No.
17/885,265
Granted
Jul 15, 2025
Kind
B2
Abstract

The present disclosure generally relates to improved handling of write commands. The host memory buffer (HMB) or other storage space can be utilized to delay execution of host write commands which will improve write performance in different use cases and will also allow having more concurrent streams than open blocks without impacting write or read performance. Generally, once a write command is received, the write command is revised as a new write command that is logically equivalent to the original write command. The revised write command is moved to the HMB along with the data. In so doing, the write command is coalesced and write command handling is improved.

Claims (38)

1. A data storage device, comprising:

a first memory device; and

a controller coupled to the first memory device, wherein the controller is configured to:

receive a write command, wherein the write command uses physical region page (PRP) entries;

determine the write command can be write coalesced, wherein the controller is configured to write coalesce by stacking data that is related to a certain stream in host memory buffer (HMB) and write the data to the first memory device without dedicating space in the controller for the write coalescing to support a number of concurrent streams that is greater than a number of available open blocks in the storage device;

allocate one or more buffers in a second memory device separate and distinct from the first memory device;

generate a revised write command from the write command, wherein the write command is an original write command, wherein the revised write command is logically equivalent to the original write command, and wherein the revised write command uses scatter-gather list (SGL) entries and not physical region page (PRP) entries; and

move data associated with the write command to at least one buffer of the allocated one or more buffers for the write coalescing.

2. The data storage device of claim 1 , wherein the controller is further configured to generate pointer lists to the at least one buffer.

3. The data storage device of claim 1 , wherein the controller is configured to update a completion queue for the write command.

4. The data storage device of claim 3 , wherein the updating occurs prior to completing the write command.

5. The data storage device of claim 3 , wherein the updating occurs after execution of the revised write command.

6. The data storage device of claim 1 , wherein the second memory device is the HMB.

7. The data storage device of claim 1 , wherein the write command is a non-volatile memory express (NVMe) write command using one or more PRP entries.

8. The data storage device of claim 1 , wherein the controller is further configured to execute the revised write command in response to either a trigger mechanism or an elapsed predetermined period of time as passed.

9. A data storage device, comprising:

a first memory device; and

a controller coupled to the first memory device, wherein the controller is configured to:

receive a write command, wherein the write command uses physical region page (PRP) entries;

revised the write command to create a revised write command, wherein the write command is an original write command, wherein the revised write command is logically equivalent to the original write command, and wherein the revised write command uses scatter-gather list (SGL) elements and not physical region page (PRP) entries;

store the revised write command in a second memory device distinct from the first memory device during write coalescing, wherein the controller is configured to write coalesce by stacking data that is related to a certain stream in host memory buffer (HMB) and write the data to the first memory device without dedicating space in the controller for the write coalescing to support a number of concurrent streams that is greater than a number of available open blocks in the storage device;

determine that a predetermined period of time has elapsed or a trigger mechanism has occurred; and

execute the revised write command for the write coalescing.

10. The data storage device of claim 9 , wherein the controller is further configured to activate hardware (HW) to execute the revised write command.

11. The data storage device of claim 10 , wherein executing the revised write command includes retrieving data associated with the revised write command from the second memory device.

12. The data storage device of claim 11 , wherein storing the revised write command in the second memory device comprises storing the revised write command and data associated with the write command in the second memory device.

13. The data storage device of claim 9 , wherein executing the revised write command comprises retrieving data associated with the write command from the second memory device and writing the data to the first memory device.

14. The data storage device of claim 13 , wherein a completion queue in a host device is updated prior to executing the revised write command.

15. The data storage device of claim 14 , wherein the completion queue is not updated after executing the revised write command.

16. A data storage device, comprising:

memory means; and

a controller coupled to the memory means, wherein the controller is configured to:

convert a write command from physical region page (PRP) entries to scatter-gather list (SGL) entries, wherein the write command is an original write command, and wherein the converted write command is logically equivalent to the original write command;

store data associated with the PRP entries and the converted write command in a host device during write coalescing, wherein the controller is configured to write coalesce by stacking data that is related to a certain stream in host memory buffer (HMB) and write the data to the memory means without dedicating space in the controller for the write coalescing to support a number of concurrent streams that is greater than a number of available open blocks in the storage device;

inform the host device that the write command is completed; and

execute the converted write command after the informing, wherein the executing comprises writing the stored data to the memory means for the write coalescing.

17. The data storage device of claim 16 , wherein the controller is configured to not inform the host device that the converted write command is executed.

18. The data storage device of claim 16 , wherein the controller is configured to execute the converted write command after receiving a flush command from the host device.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2022
From: BENISTY, SHAY; BAZARSKY, ALEXANDER; HAHN, JUDAH GAMLIEL; NAVON, ARIEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060952/0235 →
Continuity (1)
Related Publication 20240053923A1 · Feb 15, 2024
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