IP Library Granted Patent US 10,922,242
Granted Patent B2
US 10,922,242 · App. 16/450,838 · Granted Feb 16, 2021

Adaptable logical to physical tables for multiple sector pattern support

Inventors: Cory Lappi (Rochester, MN); William Jared Walker (Rochester, MN); Darin Edward Gerhart (Oronoco, MN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/1009G06F2212/657
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Quick Facts
Patent No.
US 10,922,242
App. No.
16/450,838
Granted
Feb 16, 2021
Kind
B2
Abstract

The present disclosure describes logical to physical tables that are configured to provide multiple sector support and provide for help in processing of data when a sector is mapped or unmapped. In the cases where sectors are unmapped, the present disclosure provides mechanisms to concurrently support multiple unique unmapped data patterns depending upon the specific type of unmapped sector.

Claims (44)

1. A storage device, comprising:

a memory device containing a logical to physical table for a computing arrangement, wherein the table provides a map of logical sector addresses to physical address and a mapped state of the memory device, wherein sectors of the memory device are grouped into indirection units; and

a controller coupled to the memory device, the controller is configured to:

receive a read command specifying read data at the controller for the memory device, the read command originating from a host;

determine, through the logical to physical table, if the read command received at the controller corresponds to an unmapped portion of the memory device;

perform a read of the memory device when the logical to physical table indicates a mapped sector;

determine a desired sector pattern from the logical to physical entry when the logical to physical table is unmapped;

reviewing the read command received at the controller to determine if a pattern is specified for at least one sector and that the pattern specified is different than an existing pattern for the at least one sector; and

return a specified pattern for the read data to the host.

2. The storage device of claim 1 , wherein the controller is further configured to change the existing pattern to the pattern specified when the existing pattern is different than the specified pattern.

3. The storage device of claim 2 , wherein the specified pattern corresponds to a format command.

4. The storage device of claim 2 , wherein the specified pattern corresponds to an unmap command.

5. The storage device of claim 2 , wherein the specified pattern corresponds to a key change command.

6. The storage device of claim 2 , wherein the specified pattern corresponds to a sanitize command.

7. The storage device of claim 2 , wherein the controller is configured to set all affected L2P entries to M=0.

8. A storage device, comprising:

a memory device containing a logical to physical table for a computing arrangement, wherein the table provides a map of logical sector addresses to physical address and a mapped state of the memory device, wherein sectors of the memory device are grouped into indirection units; and

a controller coupled to the memory device, the controller is configured to:

receive a TCG band command;

update TCG band's key change pattern buffer with new key change pattern;

update TCG's band unmap pattern; and

update TCG band's band adjustment pattern buffer with new band adjustment pattern.

9. The storage device of claim 8 , where the controller is further configured to receive an erase band/key change command.

10. The storage device of claim 9 , wherein the controller is further configured to set all band's L2P entries to M=0 and point to band's key change pattern.

11. The storage device of claim 8 , wherein the controller is further configured to receive an unmap command.

12. The storage device of claim 11 , wherein the controller is further configured to set all band's L2P entries to M=0 and point to band's unmap pattern.

13. The storage device of claim 8 , wherein the controller is further configured to receive a band adjustment command.

14. The storage device of claim 13 , wherein the controller is further configured to set all band's L2P entries to M=0 and point to band's band adjustment pattern.

15. A storage device, comprising:

a memory device;

means for providing a logical to physical table for a computing arrangement, wherein the table provides a map of logical sector addresses to physical address and a mapped state of the memory device, wherein sectors of the memory device are grouped into indirection units;

means for receiving a read command at a controller for the memory device, the command originating from a host;

means for determining, through a logical to physical table, that the read command received at the controller corresponds to an unmapped portion of the memory device;

means for determining a desired sector pattern from the logical to physical entry;

means for reviewing the command received at the controller to determine if the desired sector pattern is specified for at least one sector and that the desired sector pattern specified is different than an existing pattern for the at least one sector; and

means for changing the existing pattern to the pattern specified when the existing pattern is different than the pattern specified.

16. The storage device of claim 15 , further comprising:

means for receiving a read command specifying read data at a controller for the memory device, the read command originating from a host;

means for determining if the read command received at the controller for the memory device corresponds to an unmapped portion of the memory device; and

means for performing a read of the memory device when the logical to physical table indicates a mapped sector.

17. The storage device of claim 16 , further comprising:

means for returning the pattern specified for the read data to the host.

18. The storage device of claim 15 , further comprising means to set all L2P entries to M=0.

19. The storage device of claim 18 , further comprising means to point to a key change pattern or a sanitize pattern or an unmap pattern.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2019
From: LAPPI, CORY; WALKER, WILLIAM JARED; GERHART, DARIN EDWARD
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049637/0014 →
Continuity (2)
Provisional Application 62743512 · Oct 9, 2018
Related Publication 20200110709A1 · Apr 9, 2020
Cited By (2)
US 12,204,753 US 12,368,586