IP Library Granted Patent US 11,941,269
Granted Patent B2
US 11,941,269 · App. 17/701,348 · Granted Mar 26, 2024

Data storage device with enhanced power mode management

Inventors: Niles Yang (Mountain View, CA); Sahil Sharma (San Jose, CA); Phil D. Reusswig (Santa Clara, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0634G06F1/3206G06F3/0625G06F3/0679
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Quick Facts
Patent No.
US 11,941,269
App. No.
17/701,348
Granted
Mar 26, 2024
Kind
B2
Abstract

A data storage device includes a non-volatile memory device having one or more memory dies and each of the memory dies include a plurality of input-output (I/O) lines. The data storage device further includes a controller. The controller is configured to receive an instruction to enter a low-power operating mode. Entering the low-power operating mode includes removing power from the one or more memory dies, providing an output signal toggling between a logic high and a logic low at a predetermined frequency to the plurality of I/O lines for a predetermined period of time, and operating in the low-power operating mode upon the expiration of the predetermined period of time.

Claims (50)

1. A data storage device, comprising:

a non-volatile memory device including one or more memory dies, wherein each of the one or more memory dies include a plurality of input-output (I/O) lines; and

a controller configured to:

enter a low-power operating mode by:

removing power from the one or more memory dies,

providing an output signal toggling between a logic high and a logic low at a predetermined frequency to the plurality of I/O lines for a predetermined period of time, and

operating in the low-power operating mode upon an expiration of the predetermined period of time.

2. The data storage device of claim 1 , further comprising a power supply circuit configured to provide power to the one or more memory dies.

3. The data storage device of claim 2 , wherein the controller is further configured to:

activate a write protect input of the non-volatile memory device to write protect the one or more memory dies upon entering the low-power operating mode;

apply a lower-level voltage to one or more power rails of the non-volatile memory device using the power supply circuit while in the low-power mode; and

maintain the activation of the write protect input and the application of the lower-level voltage while in the low-power operating mode,

wherein the lower-level voltage is less than a normal operating mode voltage.

4. The data storage device of claim 3 , wherein the lower-level voltage is 20% of the normal operating mode voltage.

5. The data storage device of claim 3 , wherein the application of the lower-level voltage to the one or more power rails reduces a time required to enter a normal operation mode by 20% versus not applying the lower-level voltage to the one or more power rails.

6. The data storage device of claim 1 , wherein the predetermined frequency is greater than 100 kHz.

7. The data storage device of claim 1 , wherein toggling the I/O lines reduces a time required to enter the low-power operating mode by 20% versus when not toggling the I/O lines.

8. A method performed by a data storage device having a controller coupled to a non-volatile memory device, the method comprising:

receiving an instruction to enter a low-power operating mode; and

entering the low-power operating mode by:

removing power from one or more memory dies of the non-volatile memory device,

providing an output signal toggling between a logic high and a logic low to one or more input-output lines of the non-volatile memory device for a predetermined period of time, and

operating in the low-power operating mode upon an expiration of the predetermined period of time.

9. The method of claim 8 , wherein the toggling is performed at a predetermined frequency.

10. The method of claim 9 , wherein the predetermined frequency is greater than 100 kHz.

11. The method of claim 8 , further comprising:

activating a write protect input of the non-volatile memory device;

applying a lower-level voltage to one or more power rails of the non-volatile memory device; and

maintaining the activation of the write protect input and the application of the lower-level voltage while in the low-power operating mode,

wherein the lower-level voltage is less than a normal operating mode voltage.

12. The method of claim 11 , wherein the lower-level voltage is 20% of the normal operating mode voltage.

13. The method of claim 11 , wherein application of the lower-level voltage to the one or more power rails reduces a time to enter a normal operation mode by 20% voltage versus not applying the lower-level voltage to the one or more power rails.

14. The method of claim 8 , wherein toggling the input-output lines reduces a time required to enter the low-power operating mode by 20% versus when not toggling the I/O lines.

15. A data storage device, comprising:

a non-volatile memory device including one or more memory dies, wherein each of the one or more memory dies include a plurality of input-output (I/O) lines;

a power supply circuit configured to provide power to the data storage device; and

a controller configured to:

receive an instruction to enter a low-power operating mode,

enter the low-power operating mode by:

removing power from the one or more memory dies

providing an output signal toggling between a first voltage level and a second voltage level at a predetermined frequency to the plurality of I/O lines, and

removing the output signal upon a voltage of the plurality of I/O lines falling below a predetermined threshold;

activate a write protect input of the non-volatile memory device to write protect the one or more memory dies upon entering the low-power operating mode,

apply a lower-level voltage to one or more power rails of the non-volatile memory device using the power supply circuit, and

maintain the activation of the write protect input and the application of the lower-level voltage while in the low-power operating mode,

wherein the lower-level voltage is less than a normal operating mode voltage.

16. The data storage device of claim 15 , wherein the predetermined frequency is at least 100 kHz.

17. The data storage device of claim 15 , wherein the lower-level voltage is 20% of the normal operating mode voltage.

18. The data storage device of claim 15 , wherein the application of the lower-level voltage to the one or more power rails reduces a time required to enter a normal operation mode by 20% versus not applying the low-level voltage to the one or more power rails.

19. The data storage device of claim 15 , wherein toggling the I/O lines reduces a time required to enter the low-power operating mode by 20% versus when not toggling the I/O lines.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 22, 2022
From: YANG, NILES; SHARMA, SAHIL; REUSSWIG, PHIL D.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059344/0439 →