Block erase type detection using bit count check
A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to determine that a power loss event has occurred, determine that one or more blocks are in an erased state, examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block, and place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block. The controller is further configured to determine a first bit count of page0 for a SLC voltage for the block, determine a second bit count of page1 for a TLC voltage for the block, and classify the block as either a SLC erased block or a TLC erased block.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
determine that a power loss event has occurred;
determine that one or more blocks are in an erased state;
examine a block of the one or more blocks to determine whether the block is a SLC erased block or a TLC erased block; and
place the block in a SLC pre-erase heap if the block is the SLC erased block or in a TLC pre-erase heap if the block is the TLC erased block.
2. The data storage device of claim 1 , wherein the block is a hybrid block, and wherein the hybrid block is configured to store either SLC data or TLC data.
3. The data storage device of claim 1 , wherein the controller is further configured to check a first bit count at a first erase voltage threshold on page0 of the block.
4. The data storage device of claim 3 , wherein, based upon the first erase voltage threshold, the controller is further configured to classify the block as the TLC erased block or the SLC erased block.
5. The data storage device of claim 4 , wherein the controller is further configured to place the block in the TLC pre-erase heap upon classifying the block as the TLC erased block.
6. The data storage device of claim 3 , wherein the controller is further configured to check a second bit count at a second erase voltage threshold on page1 of the block.
7. The data storage device of claim 6 , wherein the checking occurs after determining that the first bit count is above a bit count threshold for the first erase voltage threshold.
8. The data storage device of claim 6 , wherein, based upon the second erase voltage threshold, the controller is further configured to classify the block as the TLC erased block or the SLC erased block.
9. The data storage device of claim 1 , wherein the controller is further configured to determine if erasing is needed upon the examining.
10. The data storage device of claim 9 , wherein the controller is further configured to erase the block when the block cannot be determined as the SLC erased block or the TLC erased block.
11. The data storage device of claim 10 , wherein the controller is further configured to flash fill the block prior to the erasing.
12. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
determine that a block is an erased state;
determine a first bit count of page0 for a SLC voltage for the block;
determine a second bit count of page1 for a TLC voltage for the block; and
classify the block as either a SLC erased block or a TLC erased block.
13. The data storage device of claim 12 , wherein the SLC voltage is a SLC erase voltage.
14. The data storage device of claim 12 , wherein the TLC voltage is a TLC erase voltage.
15. The data storage device of claim 12 , wherein the first bit count is above a first threshold and the second bit count is above a second threshold, and wherein the block is classified as the SLC erased block.
16. The data storage device of claim 12 , wherein the first bit count is above a first threshold and the second bit count is below a second threshold.
17. The data storage device of claim 16 , wherein the block is defined as a TLC program abort on the page0 , wherein the block is TLC erased, and wherein the block placed in a TLC non-pre erased heap.
18. A data storage device, comprising:
memory means; and
a controller coupled to the memory means, the controller configured to:
determine that a block is in an erased state;
attempt to determine that the block is a SLC erased block or a TLC erased block;
flash fill the block; and
erase the block.
19. The data storage device of claim 18 , wherein the flash filling occurs after the attempting to determine is inconclusive.
20. The data storage device of claim 18 , wherein the controller is further configured to place the block in either a SLC heap or a TLC heap.