IP Library Granted Patent US 10,275,378
Granted Patent B2
US 10,275,378 · App. 15/452,039 · Granted Apr 30, 2019

Data buffer pointer fetching for direct memory access

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,275,378
App. No.
15/452,039
Granted
Apr 30, 2019
Kind
B2
Abstract

Technology is described herein for operating non-volatile storage. In one aspect, a memory controller fetches pointers to data buffers in host system memory just-in-time. For example, just before the memory system is ready perform a DMA the pointers may be fetched. The data buffer pointers may be NVMe Physical Region Page (PRP) entries in a PRP list. The same data buffer pointer need not be fetched more than once. For example, responsive to the non-volatile memory system determining that a data buffer pointer might be needed a second time (e.g., for a different DMA), that data buffer pointer is saved such that it can be re-used. In one aspect, if a DMA does access all of a host data buffer, the pointer to that buffer is saved so that it does not need to be fetched again.

Claims (67)

1. A non-volatile storage system, comprising:

a plurality of non-volatile memory cells;

command context storage; and

a control circuit in communication with the command context storage and the plurality of non-volatile memory cells, the control circuit configured to:

access a command from a host system to access non-volatile memory cells in the non-volatile storage system, the command comprising a first list pointer to a first list comprising data buffer pointers to data buffers in the host system;

store, in the command context storage, the first list pointer;

store, in the command context storage, a second list pointer to a second list of data buffer pointers in the host system;

responsive to a determination that a data buffer pointer to be used for a direct memory access (DMA) to respond to the command is within either the first list or the second list, use either the first list pointer or the second list pointer to fetch the data buffer pointer;

responsive to a determination that the data buffer pointer is not within either the first list or the second list, fetch a third list pointer from host system memory and use the third list pointer to fetch the data buffer pointer; and

perform a direct memory access (DMA) between the non-volatile storage system and the data buffer in the host system pointed to by the fetched data buffer pointer.

2. The non-volatile storage system of claim 1 , wherein the control circuit is further configured to:

store the third list pointer in the command context storage, wherein the third list pointer overwrites either the first list pointer or the second list pointer; and

store an index of the third list pointer in the command context storage.

3. The non-volatile storage system of claim 1 , further comprising:

a separate data buffer pointer storage for each of a plurality of memory dies in the non-volatile storage system, wherein the control circuit is further configured to store data buffer pointers to host system data buffers in the respective data buffer pointer storages for the plurality of memory dies.

4. The non-volatile storage system of claim 3 , wherein the control circuit is further configured to perform DMAs with respect to a data buffer pointer storage of a given memory die out of order with respect to data buffer pointer storage of other memory dies.

5. The non-volatile storage system of claim 1 , wherein the data buffer pointer is a physical region page (PRP) pointer in a non-volatile memory express (NVMe) interface.

6. The non-volatile storage system of claim 1 , wherein:

the control circuit is configured to fetch the data buffer pointer along with other data buffer pointers to host system data buffers over a Peripheral Computer Interface Express (PCIe) bus;

the command is associated with multiple lists of data buffer pointers in memory of the host system; and

the control circuit is further configured to fetch only data buffer pointers that fit in a single Transaction Layer Packet (TLP) packet over the PCIe bus.

7. The non-volatile storage system of claim 1 , wherein:

the command is a read command; and

the control circuit is further configured to fetch the data buffer pointer after the control circuit issues a read operation to a memory die in the non-volatile storage system to satisfy the read command but prior to data read from the memory die in response to the read operation being ready to transfer to the host system.

8. The non-volatile storage system of claim 1 , wherein the control circuit is further configured to discard the data buffer pointer responsive to a determination that, the DMA accessed the entire host data buffer pointed to by the data buffer pointer.

9. The non-volatile storage system of claim 1 , wherein the control circuit is further configured to fetch the data buffer pointer from host system memory.

10. The non-volatile storage system of claim 1 , further comprising:

a memory controller; and

a storage unit coupled to the memory controller, wherein the control circuit is further configured to fetch the data buffer pointer from the storage unit coupled to the memory controller.

11. The non-volatile storage system of claim 1 , wherein the DMA is a first DMA, and wherein the control circuit is further configured to:

responsive to the first DMA not accessing the entire data buffer, save the fetched data buffer pointer into the command context storage;

access the saved data buffer pointer from command context storage; and

use the saved data buffer pointer to perform a second DMA to access a portion of the host data buffer pointed to by the data buffer pointer that the first DMA did not access.

12. A method of operating a non-volatile storage system, the method comprising:

accessing a command from a host system to access non-volatile memory cells in the non-volatile storage system, the command comprising a first field having a data buffer pointer to a data buffer and a second field having a first list pointer to a first list of data buffer pointers to data buffers in the host system;

storing, in command context storage in the non-volatile storage system, the first list pointer;

storing, in the command context storage, a second list pointer to a second list of data buffer pointers in the host system;

responsive to a determination that first data buffer pointers to be used for first direct memory accesses (DMAs) with respect to a first read operation or a first write operation of the non-volatile memory cells to respond to the command are within either the first list or the second list, using either the first list pointer or the second list pointer to fetch the first data buffer pointers, wherein the first data buffer pointers are fetched from the host system to storage in the non-volatile storage system;

responsive to a determination that second data buffer pointers to be used for second DMAs with respect to a second read operation or a second write operation of the non-volatile memory cells to respond to the command are not within either the first list or the second list, fetching a third list pointer from host system memory and using the third list pointer to fetch the second data buffer pointers, wherein the second data buffer pointers are fetched from the host system to storage in the non-volatile storage system; and

performing the first DMAs between the non-volatile storage system and the data buffers in the host system pointed to by the fetched first data buffer pointers; and

performing the second DMAs between the non-volatile storage system and the data buffers in the host system pointed to by the fetched second data buffer pointers.

13. The method of claim 12 , further comprising:

responsive to a determination that the host data buffers pointed to by the first data buffer pointers have been fully accessed by the first DMAs, discarding the first data buffer pointers.

14. The method of claim 12 , further comprising:

responsive to a particular DMA of the second DMAs accessing an entire host data buffer pointed to by a particular data buffer pointer of the second data buffer pointers, determining that the particular data buffer pointer should not be saved.

15. The method of claim 12 , wherein:

the first list pointer points to a first list of non-volatile memory express (NVMe) physical region page (PRP) entries in the host system; and

the second list pointer points to a second list of NVMe PRP entries in the host system.

16. The method of claim 12 , wherein using the third list pointer to fetch the second data buffer pointers comprises fetching the second data buffer pointers to data buffers of the host system after initiating the second read operation but before data read from a memory die is ready to be transferred to the host system.

17. The method of claim 12 , further comprising:

saving data buffer pointers to host system data buffers in separate data buffer storage in the non-volatile storage system for each of a plurality of memory dies in the non-volatile storage system.

18. The method of claim 12 , wherein using either the first list pointer or the second list pointer to fetch the first data buffer pointers and using the third list pointer to fetch the second data buffer pointers comprises:

fetching only data buffer pointers that fit in a single Transaction Layer Packet (TLP) packet over a PCIe bus.

19. A non-volatile storage system, comprising:

a plurality of memory dies of non-volatile memory cells;

means for accessing a command from a host system to access the non-volatile memory cells;

means for parsing the command to determine whether the command has a first field having a pointer to a data buffer and a second field having a first list pointer to a first list of data buffer pointers to data buffers in a host system;

means for storing the first list pointer;

means for storing a second list pointer to a second list of data buffer pointers in the host system;

means for initiating a memory array operation of non-volatile memory cells in a memory die in the non-volatile storage system responsive to the command;

means for using either the first list pointer or the second list pointer to access data buffer pointers to data buffers of the host system to be used for direct memory accesses (DMAs) of memory in the host system with respect to the memory array operation responsive to a determination that the data buffer pointers are within either the first list or the second list;

means for fetching a third list pointer from host system memory and using the third list pointer to access the data buffer pointers responsive to a determination that the data buffer pointers are not within either the first list or the second list and

means for performing the DMAs between the non-volatile storage system and the data buffers in the host system pointed to by the accessed data buffer pointers.

20. The method of claim 12 , further comprising:

responsive to a first DMA for a particular data buffer pointer of the first data buffer pointers not accessing the entire data buffer pointed to by the particular data buffer pointer, saving the particular data buffer pointer into the command context storage;

accessing the saved particular data buffer pointer from command context storage; and

using the saved particular data buffer pointer to perform a second DMA to access a portion of the host data buffer pointed to by the particular data buffer pointer that the first DMA for the particular data buffer pointer did not access.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2017
From: BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 041903/0836 →