Granted Patent B2

US 8,699,266 · App. 13/361,905 · Granted Apr 15, 2014

Abstract

Claims (29)

1. A method for implementing data write for multi-level cell (MLC) memory comprising:

identifying a voltage baseline of a prior write; and

responsive to the identified voltage baseline, performing a data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding for data being written to the MLC memory.

2. The method for implementing data write as recited in claim 1 wherein identifying the voltage baseline of the prior write includes reading MLC memory cells before performing the data write.

3. The method for implementing data write as recited in claim 1 wherein identifying the voltage baseline of the prior write includes maintaining predefined parameter information on MLC memory cells; said predefined parameter information including said voltage baseline.

4. The method for implementing data write as recited in claim 3 includes updating said voltage baseline after each write to a cell and after each cell erase.

5. The method for implementing data write as recited in claim 1 wherein performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes using a run-length limited (RLL) code.

6. The method for implementing data write as recited in claim 1 wherein performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes storing flags to indicate occurrences of illegal data combination.

7. The method for implementing data write as recited in claim 1 wherein performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes periodically writing references cells at specified voltage levels to keep track of said baseline voltage.

8. The method for implementing data write as recited in claim 1 wherein performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes providing adjustable threshold level resolution of the threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding.

9. The method for implementing data write as recited in claim 1 wherein performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes downgrading a state-level of the threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding.

10. The method for implementing data write as recited in claim 1 wherein performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes changing from a 4-state moving baseline memory data code to a 2-state moving baseline memory data code.

11. The method for implementing data write as recited in claim 1 wherein performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes providing adjustable resolution of the threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding using a set number of write cycles before performing a partial erase of the MLC memory.

12. An apparatus for implementing data write for multi-level cell (MLC) memory comprising:

a controller;

said controller identifying a voltage baseline of a prior write; and

said controller responsive to the identified voltage baseline, performing a data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding for data being written to the MLC memory.

13. The apparatus as recited in claim 12 includes control code stored on a computer readable medium, and wherein said controller uses said control code for implementing data write.

14. The apparatus as recited in claim 12 wherein said controller identifying the voltage baseline of the prior write includes said controller reading MLC memory cells before performing the data write.

15. The apparatus as recited in claim 12 wherein said controller identifying the voltage baseline of the prior write includes said controller maintaining predefined parameter information on MLC memory cells; said predefined parameter information including said voltage baseline.

16. The apparatus as recited in claim 12 , wherein said controller performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes said controller using a run-length limited (RLL) code.

17. The apparatus as recited in claim 12 , wherein said controller performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes said controller providing adjustable threshold level resolution of the threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding and said controller providing an adjustable number of write cycles before performing a partial erase of the MLC memory.

18. A data storage device comprising:

a multi-level cell memory;

a controller using a moving baseline memory data encoding control for data write;

said controller identifying a voltage baseline of a prior write; and

said controller responsive to the identified voltage baseline, performing a data write using the threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding control for data being written to the MLC memory.

19. The data storage device as recited in claim 18 , wherein said controller identifying the voltage baseline of the prior write includes said controller maintaining predefined parameter information including said voltage baseline.

20. The data storage device as recited in claim 18 , wherein said controller performing data write using threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding includes said controller providing adjustable threshold level resolution of the threshold-voltage-drift or resistance-drift tolerant moving baseline memory data encoding.

Assignments (12)