Determine link startup sequence (LSS) type using reference clock frequency and attribute
The present disclosure generally relates to utilizing the host clock signal frequency to determine whether to operate in the default pulse width modulation (PWM) link startup sequence (LSS), be changed to high speed (HS) LSS by a host device capable of operating in either PWM LSS or HS LSS, or ignore the data storage device attributes of operating in PWM LSS and instead operate according to HS LSS. In so doing, the data storage device is adaptable to work with older generation UFS host devices as well as current and future generation UFS host devices.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
set first default link attributes to a first frequency at a first power on, wherein the first default link attributes is a pulse width modulation (PWM) link startup sequence (LSS);
receive a host reference clock signal from a host device, wherein the host reference clock signal has a second frequency and second default link attributes different from the first default link attributes, wherein the second default link attributes is a high speed (HS) LSS;
determine that the second frequency is higher than the first frequency;
ignore the first frequency;
operate at the second frequency while maintaining the first default link attributes; and
change from the first default link attributes to the second default link attributes at a second power on.
2. The data storage device of claim 1 , further comprising:
a printed circuit board (PCB);
a pin; and
a resistor.
3. The data storage device of claim 2 , wherein the resistor is not directly coupled to the host device.
4. The data storage device of claim 2 , wherein the pin is coupled to the resistor.
5. The data storage device of claim 4 , wherein the resistor is coupled to the PCB.
6. The data storage device of claim 2 , wherein the resistor is configured to either pull up or pull down to create a fixed signal, wherein the fixed signal corresponds to either a low frequency corresponding to first frequency or a high frequency corresponding to the second frequency.
7. The data storage device of claim 1 , wherein the host device is an application processor (AP).
8. The data storage device of claim 1 , wherein first frequency operates at 19.4 MHZ, 26 MHZ, 38.4 MHZ, or 52 MHz.
9. The data storage device of claim 1 , wherein the second frequency operates at 78.6 MHz or 104 MHz.
10. The data storage device of claim 1 , wherein the host device has an internal indication for whether to start in the second frequency or the first frequency.
11. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, the controller configured to:
set default link attributes to a first frequency at a first power on, wherein the default link attributes is a PWM LSS;
receive a host reference clock signal from a host device, wherein the host reference clock signal has a second frequency and a second link attributes different from the default link attributes;
receive instructions from the host device to change the link attributes to the second frequency;
change the default link attributes to the second link attributes;
operate as the second frequency with the second link attributes at a second power on, based on the change, wherein the second link attributes is a HS LSS.
12. The data storage device of claim 11 , wherein the host device is a 4th Generation UFS device.
13. The data storage device of claim 11 , comprising a register.
14. The data storage device of claim 13 , wherein changing the default link attributes is performed by a LSS register.
15. The data storage device of claim 11 , wherein changing the default link attributes is performed by a resistor and a pin.
16. The data storage device of claim 11 , wherein the host device is an application processor (AP), wherein the data storage device comprises a printed circuit board (PCB) and either:
a resistor and a pin; or
a register.