High density spin torque three dimensional (3D) memory arrays addressed with microwave current
View Patent ↗One embodiment of the present invention includes a three dimensional memory array having a plurality of memory elements coupled to form the array through a single top lead and a single bottom lead, each memory element including a magnetic free layer in which non-volatile data can be stored, wherein each memory element possesses unique resonant frequencies associated with each digital memory state, thereby enabling frequency addressing during parallel write and read operations, each memory element further including a fixed layer and a spacer formed between the free layer and the fixed layer.
1. A three-dimensional (3-D) nonvolatile memory array comprising:
a plurality of memory elements arranged in a 3-D configuration wherein each memory element is selectable based on a unique resonant frequency, wherein the plurality of memory elements are arranged in stacks, each stack having a different shape anisotropy than the other stacks, the plurality of memory elements further arranged in layers with each layer having a different magnetocrystalline anisotropy (MCA) than the other layers.
2. A three-dimensional (3-D) memory array, as recited in claim 1 , further including an insulation layer separating each stack.
3. A three-dimensional (3-D) memory array, as recited in claim 2 , further including an insulation layer separating the memory elements of a layer.
4. A three-dimensional (3-D) memory array, as recited in claim 3 , further including a top lead formed on top of the plurality of memory elements through which current is provided thereto.
5. A three-dimensional (3-D) memory array, as recited in claim 4 , further including a bottom lead formed on the bottom of the plurality of memory elements.
6. A three-dimensional (3-D) memory array, as recited in claim 5 , further including a polarization layer formed on top of the plurality of memory elements and below the top lead.
7. A three-dimensional (3-D) memory array, as recited in claim 1 , wherein the memory elements of the plurality of memory elements comprise a fixed layer, a spacer formed on top of the fixed layer and at least one free layer formed on top of the spacer.