ERROR RATE MANAGEMENT IN NON-UNIFORM MEMORY ARRAYS
A plurality of control circuits are configured to individually connect to arrays that each include a plurality of non-volatile memory cells. Each non-volatile memory cell includes a programmable resistive element. Each control circuit is configured with an individual address offset. The plurality of control circuits are configured to: receive a read address from a memory controller in parallel, apply the respective individual address offsets to the read address to generate respective offset addresses, read portions of data from the respective offset addresses and send the data read from the offset addresses to the memory controller to perform Error Correction Code (ECC) decoding of the portions of data.
1 . An apparatus, comprising:
a plurality of control circuits configured to individually connect to arrays that each include a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistive element, each control circuit configured with an individual address offset, the plurality of control circuits are configured to:
receive a read address from a memory controller in parallel;
apply the respective individual address offsets to the read address to generate respective offset addresses;
read portions of data from the respective offset addresses; and
send the data read from the offset addresses to the memory controller to perform Error Correction Code (ECC) decoding of the portions of data.
2 . The apparatus of claim 1 , wherein the plurality of control circuits includes at least a first control circuit configured to connect to a first array and a second control circuit configured to connect to a second array, the first control circuit configured with a first address offset, the second control circuit configured with a second address offset such that a first offset address generated by applying the first address offset is closer to at least one of a word line driver or a bit line driver than a second offset address generated by applying the second address offset.
3 . The apparatus of claim 2 , wherein the first control circuit and the first array are located on a first die and the second control circuit and the second array are located on a second die.
4 . The apparatus of claim 2 , wherein the first control circuit is located on a first control die configured to be bonded to a first memory die containing the first array and the second control circuit is located on a second control die configured to be bonded to a second memory die containing the second array.
5 . The apparatus of claim 1 , wherein the plurality of control circuits includes N control circuits each connected to a respective array, the N control circuits applying N different address offsets.
6 . The apparatus of claim 5 , wherein the N different address offsets are configured to cause reading each array at a different respective location with respect to at least one of a word line driver or a bit line driver.
7 . The apparatus of claim 6 , wherein the N different address offsets are configured to cause reading each array at different respective locations that are equally spaced apart from each other.
8 . The apparatus of claim 1 , wherein each array includes a plurality of banks, each bank includes a plurality of modules that are configured to be read in parallel and the individual address offset includes at least one of a word line offset or a bit line offset that causes reading of every module of a bank indicated by the read command at a common offset address.
9 . The apparatus of claim 1 , wherein each array includes a plurality of banks, each bank includes a plurality of modules that are configured to be read in parallel and the individual address offset causes reading of different modules of a bank indicated by the read command at different offset addresses.
10 . The apparatus of claim 1 , wherein each control circuit includes a register to store a corresponding individual address offset.
11 . A method, comprising:
sending a read address to a plurality of memory dies applying a plurality of address offsets to the read address to generate a plurality of respective offset addresses in the plurality of memory dies including at least a first offset address in a first memory die and a second offset address in a second memory die;
reading a portion of data from a respective offset address of the memory dies including reading a first portion of data from the first offset address and reading a second portion of data from the second offset address; and
decoding the portions of data of all memory dies of the plurality of memory dies including the first and second portions together.
12 . The method of claim 11 , wherein the plurality of memory dies includes N memory dies, each memory die including a respective array, the N memory dies applying N different address offsets such that the portion of data is read from a different respective location in each memory die.
13 . The method of claim 11 , wherein the read address is received by the plurality of memory dies in parallel through a common communication channel between a memory controller and the plurality of memory dies.
14 . The method of claim 13 , wherein the portions of data from the plurality of memory dies are sent in parallel through a plurality of communication channels between the plurality of memory dies and the memory controller.
15 . The method of claim 11 , further comprising:
receiving, by the plurality of memory dies, a write address and write data;
applying, by each memory die, the respective individual address offsets to the write address to generate respective offset addresses; and
writing the write data at the respective offset addresses in the plurality of memory dies.
16 . The method of claim 11 , further comprising selecting the respective individual address offsets according to the number of memory dies and locations of word line and bit line drivers with respect to addresses in the dies.
17 . The method of claim 16 , wherein applying respective individual address offsets to the read address to generate a plurality of respective offset addresses in the plurality of memory dies includes, in a first memory die, applying different address offsets to read different modules of the first memory die in parallel.
18 . A system, comprising:
an Error Correction Code (ECC) circuit;
a first array that includes a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistive element;
means for applying a first address offset to read and write commands from the memory controller directed to a target address to obtain a first offset address, read data from the first offset address in the first array and send data from the first offset address in the first array to the ECC circuit for ECC decoding;
a second array that includes a plurality of non-volatile memory cells, each non-volatile memory cell comprising a programmable resistive element; and
means for applying a second address offset to read and write commands from the memory controller directed to the target address to obtain a second offset address, read data from the second offset address in the second array and send data from the second offset address in the second array to the ECC circuit for ECC decoding with the data from the first offset address in the first array.
19 . The system of claim 18 , wherein the first offset address is located a first distance from word line and/or bit line drivers of the first array, the second offset address is located a second distance from word line and/or bit line drivers of the second array and the first distance is less than the second distance.
20 . The system of claim 18 , wherein the first array and the means for applying the first address offset are located in a first media, the second array and the means for applying the second address offset are located in a second media and the ECC circuit is located in a memory controller die that is connected to the first media, the second media and additional media.