Data storage device and method for hiding tweak generation latency
A decryption engine can decrypt encrypted data read from a physical address in a memory of a data storage device. To decrypt the data, the decryption engine can use a tweak value that is generated from a logical address associated with the physical address. To reduce latency, the tweak value can be generated in parallel with the translation of the logical address to the physical address. The tweak value can be stored in a tweak buffer in the decryption engine until needed and can be indexed by a tag associated with a process in a host that is requesting the data. The tweak buffer can use static random-access memory (SRAM) or a content-addressable memory (CAM), for example. Other embodiments are provided.
1. A data storage device comprising:
a memory;
a memory controller comprising one or more processors, individually or in combination, configured to read encrypted data stored in a physical address in the memory;
a logical-address-to-physical-address translator configured to:
receive a read request from a host, wherein the read request comprises a logical address and a request tag, wherein the logical address is in an unencoded format;
translate the logical address to the physical address in the memory; and
provide, to the memory controller, the read request with the physical address and the request tag; and
a decryption engine comprising:
a tweak buffer comprising a content-addressable memory (CAM);
a tweak generator configured to:
receive the logical address that is in the read request from the host;
calculate a tweak value from the logical address that is in the read request from the host, wherein the tweak value is calculated in parallel to the logical address being translated to the physical address, and wherein a latency to calculate the tweak value is less than a latency to translate the physical address from the logical address; and
store the tweak value and the request tag in the tweak buffer by:
verifying that there is no match for the request tag in the tweak buffer; and
in response to verifying that there is no match for the request tag in the tweak buffer, initializing a CAM entry in the tweak buffer that associates the tweak value with the request tag; and
a decrypter configured to:
receive the encrypted data and the request tag from the memory controller; and
in response to receiving the encrypted data and the request tag from the memory controller:
use the request tag to attempt to retrieve the tweak value from the tweak buffer;
in response to the attempt to retrieve the tweak value from the tweak buffer being successful:
use the tweak value to decrypt the encrypted data; and
reset the request tag of the CAM entry to an invalid value; and
in response to the attempt to retrieve the tweak value from the tweak buffer being unsuccessful, which indicates that the tweak calculation is not finished:
re-attempt to retrieve the tweak value from the tweak buffer; and
block decryption of the encrypted data until the re-attempt to retrieve the tweak value from the tweak buffer is successful.
2. The data storage device of claim 1 , wherein the decrypter comprises an AES-XTS decryption engine, wherein AES-XTS refers to Advanced Encryption Standard (AES) cryptography that uses an exclusive-or (XOR) Encrypt XOR (XEX) Tweakable Block Cipher with Ciphertext Stealing (XTS).
3. The data storage device of claim 1 , wherein the memory controller comprises ordering logic.
4. The data storage device of claim 1 , wherein the memory comprises magnetoresistive random-access memory (MRAM).
5. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.
6. In a decryption engine in a data storage device, a method comprising:
receiving a read request from a host, wherein the read request comprises a logical address and a request tag, wherein the logical address is in an unencoded format;
translating the logical address to a physical address of a memory of the data storage device;
while the data storage device is translating the logical address to the physical address, using the logical address that is in the read request from the host to generate a value needed to decrypt encrypted data stored at the physical address in the memory, wherein a latency to calculate the value is less than a latency to translate the logical address to the physical address;
storing the value in a buffer in the decryption engine, wherein the buffer comprises a content-addressable memory (CAM), and wherein storing the value in the buffer comprises:
verifying that there is no match for the request tag in the buffer; and
in response to verifying that there is no match for the request tag in the buffer, initializing a CAM entry in the buffer that associates the value with the request tag;
receiving the encrypted data from the memory;
attempting to retrieve the value from the buffer;
in response to the attempt to retrieve the value from the buffer being successful:
using the value to decrypt the encrypted data; and
resetting the request tag of the CAM entry to an invalid value; and
in response to the attempt to retrieve the value from the buffer being unsuccessful, which indicates that generation of the value is not finished:
re-attempting to retrieve the value from the buffer; and
blocking decryption of the encrypted data until the re-attempt to retrieve the value from the tweak is successful.
7. The method of claim 6 , wherein the value comprises a tweak value.
8. The method of claim 6 , wherein the decryption engine is configured to decrypt the encrypted data using an AES-XTS algorithm, wherein AES-XTS refers to Advanced Encryption Standard (AES) cryptography that uses an exclusive-or (XOR) Encrypt XOR (XEX) Tweakable Block Cipher with Ciphertext Stealing (XTS).
9. The method of claim 6 , wherein the decryption engine comprises a tweak generator and a data decryptor.
10. The method of claim 6 , wherein the memory comprises magnetoresistive random-access memory (MRAM).
11. The method of claim 6 , wherein the memory comprises a three-dimensional memory.
12. A data storage device comprising:
a memory; and
means for:
receiving a read request from a host, wherein the read request comprises a logical address and a request tag, wherein the logical address is in an unencoded format;
translating the logical address to a physical address of a memory of the data storage device;
while the data storage device is translating the logical address to the physical address, using the logical address that is in the read request from the host to generate a value needed to decrypt encrypted data stored at the physical address in the memory, wherein a latency to calculate the value is less than a latency to translate the logical address to the physical address;
storing the value in a buffer in the decryption engine, wherein the buffer comprises a content-addressable memory (CAM), and wherein storing the value in the buffer comprises:
verifying that there is no match for the request tag in the buffer; and
in response to verifying that there is no match for the request tag in the buffer, initializing a CAM entry in the buffer that associates the value with the request tag;
receiving the encrypted data from the memory;
attempting to retrieve the value from the buffer;
in response to the attempt to retrieve the value from the buffer being successful:
using the value to decrypt the encrypted data; and
resetting the request tag of the CAM entry to an invalid value; and
in response to the attempt to retrieve the value from the buffer being unsuccessful. which indicates that generation of the value is not finished:
re-attempting to retrieve the value from the buffer; and
blocking decryption of the encrypted data until the re-attempt to retrieve the value from the tweak is successful.