Data storage device equipped to reduce page faults in host device
The disclosure relates in some aspects to a controller of a data storage device, such as the controller of a solid state device (SSD) having non-volatile memory (NVM). In some aspects, the controller operates to prevent or reduce page faults in the host device. In one example, an outer mapping table of a set of page tables of a host device stores pointers to an inner mapping table in the SSD controller. The pointers are provided within memory access requests sent from the host to the SSD. The inner table maps the pointers to physical addresses in the SSD. The SSD detects page faults by identifying pointers that do not have corresponding entries in the inner table. The SSD allocates physical addresses to accommodate such access requests, then executes the requests on behalf of the host device. In this manner, the page fault is transparent to the host.
1. A method for use by a controller for controlling access by a host device to a physical memory array, the method comprising:
generating a mapping table for use by the controller for storing values that map reference information received from the host device to physical memory addresses within pages of the physical memory array within a physical memory space of the controller, the reference information corresponding to physical addresses within a separate memory space of the host device and corresponding to virtual addresses within the physical memory space of the controller, with the physical memory space of the controller transparent to the host;
receiving a memory access request from the host device that provides particular reference information for the mapping table of the controller;
converting the particular reference information received from the host device to a corresponding physical memory address within the physical memory space of the controller by using the particular reference information as a virtual address for conversion to the corresponding physical address within the physical memory space of the controller using the mapping table of the controller;
allocating one or more of the pages of the physical memory space of the controller to accommodate the memory access request and updating the mapping table, with the allocation of the one or more of the pages within the physical memory space of the controller transparent to the host device; and
processing the memory access request by accessing the physical memory array using the corresponding physical memory address.
2. The method of claim 1 , wherein the mapping table is one of a hierarchy of mapping tables.
3. The method of claim 1 , wherein allocating the one or more of the pages of the physical memory space of the controller comprises allocating a physical address block range.
4. The method of claim 1 , further comprising updating the mapping table to include additional entries corresponding to an additional portion of the physical memory space of the controller and notifying the host device to provide additional addresses within the memory space of the host device that refer to the additional entries of the mapping table of the controller.
5. The method of claim 1 , wherein the reference information comprises host pointers received from a page table of the host device, and wherein converting the particular reference information comprises converting the host pointers received from the page table of the host device to corresponding physical memory addresses within the physical memory space of the controller.
6. The method of claim 5 , wherein the mapping table is generated with sufficient entries so that no pointers received from the page table of the host device point to unmapped addresses.
7. The method of claim 1 , wherein the reference information corresponds to memory-mapped physical addresses within the separate memory space of the host device.
8. A data storage apparatus, comprising:
a physical memory array;
a mapping table configured to store values that map reference information received from a host device to physical memory addresses within pages of the physical memory array within a physical memory space of the data storage apparatus, the reference information corresponding to physical addresses within a separate memory space of the host device and corresponding to virtual addresses within the physical memory space of the data storage apparatus, with the physical memory space of the data storage apparatus transparent to the host;
an input controller configured to receive a memory access request from the host device that provides particular reference information for the mapping table;
a mapping controller configured to convert the particular reference information received from the host device to a corresponding physical memory address within the physical memory space of the data storage apparatus by using the particular reference information as a virtual address for conversion to the corresponding physical address within the physical memory space of the data storage apparatus using the mapping table, the mapping controller including a memory allocation controller configured to allocate one or more of the pages of the physical memory space of the data storage apparatus to accommodate the memory access request and to update the mapping table, with the allocation of the one or more of the pages within the physical memory space of the data storage apparatus transparent to the host device; and
a memory access execution controller configured to execute the memory access request by accessing the physical memory array using the corresponding physical memory address.
9. The data storage apparatus of claim 8 , wherein the memory allocation controller is further configured to allocate the one or more of the pages of the physical memory space of the data storage apparatus by allocating one or more physical address blocks.
10. The data storage apparatus of claim 8 , wherein the physical memory array comprises one or more of a non-volatile memory (NVM) and a volatile memory.
11. The data storage apparatus of claim 8 , wherein the physical memory array is a non-volatile memory (NVM) comprised of one or more of a NAND-based array, a phase-change memory (PCM) array, a magneto-resistive random access memory (MRAM) array, and a resistive random access memory (ReRAM) array.
12. The data storage apparatus of claim 8 , wherein the reference information comprises host pointers from a page table of the host device, and wherein the mapping controller is further configured to convert particular host pointers received from the page table of the host device to corresponding physical memory addresses within the physical memory space of the data storage apparatus.
13. The data storage apparatus of claim 12 , wherein the mapping table is configured with sufficient entries so that no pointers received from the page table of the host device point to unmapped addresses.
14. The data storage apparatus of claim 8 , wherein the memory allocation controller is further configured to update the mapping table without notifying the host device.
15. The data storage apparatus of claim 8 , wherein the reference information corresponds to memory-mapped physical addresses within the separate memory space of the host device.
16. A data storage apparatus, comprising:
a physical memory array;
a mapping table configured to store values that map pointers received from a host device to physical memory addresses within pages of the physical memory array within a physical memory space of the data storage apparatus, the pointers corresponding to physical addresses within a separate memory space of the host device and corresponding to virtual addresses within the physical memory space of the data storage apparatus, with the physical memory space of the data storage apparatus transparent to the host; and
a processor configured to
receive a memory access request from the host device that provides a particular pointer into the mapping table,
convert the particular pointer received from the host device to a corresponding physical memory address within the physical memory space of the data storage apparatus by using the particular pointer as a virtual address for conversion to the corresponding physical address within the physical memory space of the data storage apparatus using the mapping table, including allocating one or more of the pages of the physical memory space of the data storage apparatus to accommodate the memory access request and updating the mapping table, with the allocation of the one or more of the pages within the physical memory space of the data storage apparatus transparent to the host device, and
process the memory access request on behalf of the host device by accessing the physical memory array using the corresponding physical memory address.
17. The data storage apparatus of claim 16 , wherein the mapping table is one of a hierarchy of mapping tables.
18. The data storage apparatus of claim 17 , wherein the hierarchy of mapping tables comprises a multi-level page table.
19. The data storage apparatus of claim 16 , wherein the processor is configured to allocate the one or more of the pages of the physical memory space of the data storage apparatus by allocating a physical address block.
20. The data storage apparatus of claim 16 , wherein the physical memory array comprises one or more of a non-volatile memory (NVM) and a volatile memory.
21. The data storage apparatus of claim 16 , wherein the pointers comprise host pointers from a page table of the host device, and wherein the processor is further configured to convert particular host pointers received from the page table of the host device to corresponding physical memory addresses within the physical memory space of the data storage apparatus.
22. The data storage apparatus of claim 21 , wherein the mapping table is configured with sufficient entries so that no pointers received from the page table of the host device point to unmapped addresses.
23. The data storage apparatus of claim 16 , wherein the processor is further configured to update the mapping table without notifying the host device.
24. The data storage apparatus of claim 16 , wherein the pointers correspond to memory-mapped physical addresses within the separate memory space of the host device.
25. An apparatus of a data storage device for controlling access by a host device to a physical memory array of the data storage device, the apparatus comprising:
means for configuring a mapping component of a controller of the data storage device to map pointers received from the host device to physical memory addresses within pages of the physical memory array within a physical memory space of the data storage device, where the pointers correspond to physical addresses within a separate memory space of the host device and corresponding to virtual addresses within the physical memory space of the data storage device, with the physical memory space of the data storage device transparent to the host device;
means for inputting a memory access request from the host device that provides a particular pointer into the mapping component of the controller;
means for converting the particular pointer input from the host device to a corresponding physical memory address within the physical memory space of the data storage device by using the particular pointer as a virtual address for conversion to the corresponding physical address within the physical memory space of the data storage device using the mapping component of the controller, including allocating one or more of the pages of the physical memory space of the data storage device to accommodate the memory access request and updating the mapping component, with the allocation of the one or more of the pages within the physical memory space of the data storage device transparent to the host device; and
means for processing the memory access request on behalf of the host device by accessing the physical memory array using the corresponding physical memory address.