IP Library Granted Patent US 12,051,660
Granted Patent B2
US 12,051,660 · App. 17/514,771 · Granted Jul 30, 2024

Wire bond pad design for compact stacked-die package

Inventors: Xuyi Yang (Shanghai, CN); Fuqiang Xiao (Shanghai, CN); Cong Zhang (Shanghai, CN); Kuo-Chien Wang (Zhubei, TW); Chin-Tien Chiu (Taichung, TW)
Assignee: Western Digital Technologies, Inc.
H01L24/05H01L24/03H01L24/43H01L24/45H01L25/0657H01L25/50H01L2224/4503
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Quick Facts
Patent No.
US 12,051,660
App. No.
17/514,771
Granted
Jul 30, 2024
Kind
B2
Abstract

Systems, methods, and devices for 3D packaging. In some embodiments, a semiconductor package includes a first die and a second die. The first die includes a first bonding pad on a top of the first die and near a first edge of the first die. The second die includes a second bonding pad on a top of the second die and near a second edge of the second die. A pillar is located on the second bonding pad. The first die is mounted on top of the second die such that the first edge is parallel to the second edge and offset from the second edge such that the pillar is exposed. A wire is bonded to a bonding surface of the pillar and bonded to a bonding surface of the first bonding pad.

Claims (31)

1. A method for electrically connecting stacked semiconductor dies, wherein the stacked semiconductor dies include a first die having a first bonding pad on a top surface of the first die and proximate to a first edge of the first die and a second die having a second bonding pad on a top surface of the second die and proximate to a second edge of the second die, wherein the second die is mounted on the top surface of the first die such that the second edge is parallel to and offset from the first edge such that the first bonding pad is exposed, the method comprising:

forming a redistribution layer (RDL) on the first bonding pad, wherein the RDL extends toward the first edge from the first bonding pad;

forming an electrically conductive first pillar on the first bonding pad and providing the first pillar on the RDL; and

bonding a first wire to a bonding surface of the first pillar, and bonding the first wire to a bonding surface of the second bonding pad.

2. The method of claim 1 , wherein forming the first pillar comprises plating or depositing a conductive metal on the first bonding pad.

3. The method of claim 1 , wherein the stacked semiconductor dies comprise a third die having a third bonding pad on a top surface of the third die and proximate to a third edge of the third die, wherein the third die is mounted on the top surface of the second die and the third edge is parallel to and offset from the second edge such that the second bonding pad is exposed, the method further comprising:

forming an electrically conductive second pillar on the third bonding pad; and

bonding a second wire from the second bonding pad to a bonding surface of the second pillar.

4. The method of claim 1 , wherein the bonding surface of the first pillar is level with the top surface of the second die.

5. The method of claim 1 , wherein the bonding surface of the first pillar is level with the bonding surface of the second bonding pad.

6. The method of claim 1 , wherein the first pillar extends above the top surface of the second die.

7. The method of claim 1 , wherein a third edge of the first die perpendicular to the first edge is offset from a fourth edge of the second die perpendicular to the second edge, such that a distance between the first pillar and the second bonding pad is greater than a distance between the first pillar and the second edge.

8. An apparatus for electrically connecting stacked semiconductor dies, wherein the stacked semiconductor dies include a first die having a first bonding pad on a top surface of the first die and proximate a first edge of the first die and a second die having a second bonding pad on a top surface of the second die and proximate to a second edge of the second die, wherein the second die is mounted on the top surface of the first die such that the second edge is parallel to and offset from the first edge such that the first bonding pad is exposed, the apparatus comprising:

means for forming a redistribution layer (RDL) on the first bonding pad, wherein the RDL extends toward the first edge of the first die from the first bonding pad;

means for forming an electrically conductive first pillar on the first bonding pad and means for providing the first pillar on the RDL; and

means for bonding a first wire to a bonding surface of the first pillar, and bonding the first wire to a bonding surface of the second bonding pad.

9. The apparatus of claim 8 , wherein the means for forming the first pillar is configured to plate or deposit a conductive metal on the first bonding pad.

10. The apparatus of claim 8 , wherein the stacked semiconductor dies comprise a third die having a third bonding pad on a top surface of the third die and proximate to a third edge of the third die, wherein the third die is mounted on the top surface of the second die and the third edge is parallel to and offset from the second edge such that the second bonding pad is exposed, the apparatus further comprising:

means for forming an electrically conductive second pillar on the third bonding pad; and

means for bonding a second wire from the second bonding pad to a bonding surface of the second pillar.

11. The apparatus of claim 8 , wherein the bonding surface of the first pillar is level with the top surface of the second die.

12. The apparatus of claim 8 , wherein the bonding surface of the first pillar is level with the bonding surface of the second bonding pad.

13. The apparatus of claim 8 , wherein the first pillar extends above the top surface of the second die.

14. The apparatus of claim 8 , wherein a third edge of the first die perpendicular to the first edge is offset from a fourth edge of the second die perpendicular to the second edge, such that a distance between the first pillar and the second bonding pad is greater than a distance between the first pillar and the second edge.

15. A method for electrically connecting stacked semiconductor dies, wherein the stacked semiconductor dies include a first die having a first bonding pad on a top surface of the first die and proximate to a first edge of the first die and a second die having a second bonding pad on a top surface of the second die and proximate to a second edge of the second die, wherein the second die is mounted on the top surface of the first die such that the second edge is parallel to and offset from the first edge such that the first bonding pad is exposed, the method comprising:

increasing a height of a bonding surface of the first bonding pad by forming a pillar on the first bonding pad; and

electrically connecting, by a first wire, the bonding surface of the first bonding pad to the second bonding pad.

16. The method of claim 15 , further comprising:

increasing a height of a bonding surface of a third bonding pad of a third die, the third bonding pad disposed on a top surface of the third die and proximate to a third edge of the third die, wherein the third die is mounted on the second die such that the third edge is parallel to and offset from the second edge such that the second bonding pad is exposed; and

electrically connecting, by a second wire, the second bonding pad to the bonding surface of the third bonding pad.

17. The method of claim 15 , wherein increasing the height of the bonding surface of the first bonding pad further comprises plating or depositing a conductive metal on the first bonding pad.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2023
From: YANG, XUYI; XIAO, FUQIANG; ZHANG, CONG; WANG, KUO-CHIEN; CHIU, CHIN-TIEN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 062362/0127 →