Apparatus and method for determining an operating condition of a memory cell based on cycle information
View Patent ↗Disclosed is an apparatus and method for determining a parameter for programming a non-volatile memory circuit. On receiving write or erase operation a parameter is determined as a function of a circuit characteristic associated with a memory block. An adjusted condition, for example, read or write time, or the standard deviation of voltage thresholds in a distribution of cells, is then determined as a function of the parameter, and a command provided to the memory circuit to use the parameter in the next write or erase operation performed on the memory block. The method can be triggered by an event such as P/E cycle times and the condition is dynamically adjusted to extend the life of the memory circuit.
1. A method for adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:
storing a parameter, the operating condition being a function of the parameter;
monitoring a memory operation for a trigger event, the trigger event including a programming time satisfying a threshold programming duration; and
on the trigger event, adjusting the parameter in accordance with a circuit characteristic associated with the memory block, and
providing to the memory circuit a command representative of an instruction to apply a series of voltage pulses to a group of cells in the memory block in accordance with the adjusted parameter to adjust the operating condition.
2. The method of claim 1 , wherein each pulse in the series of pulses is an incremental step pulse such that an amplitude of each pulse is incrementally increased with each increasing pulse number, starting from a start magnitude.
3. The method of claim 1 , wherein adjusting the parameter in accordance with the circuit characteristic includes indexing a lookup table by a number of P/E cycles to determine the parameter.
4. The method of claim 3 , wherein the number of P/E cycles is a range of P/E cycles, a current P/E cycle being in the range of P/E cycles.
5. The method of claim 1 , wherein the operating condition includes a voltage distribution and adjusting the operating condition includes reducing a width of an upper portion of the voltage distribution and increasing the programming time, and adjusting the parameter in accordance with a circuit characteristic includes reducing the parameter.
6. The method of claim 5 , wherein the trigger event includes the programming time reaching a minimum programming duration.
7. The method of claim 1 , wherein the operating condition includes a voltage distribution, and adjusting the operating condition includes reducing a width of a lower portion of the voltage distribution and reducing a programming time, and adjusting the parameter in accordance with a circuit characteristic includes increasing the parameter.
8. The method of claim 1 , wherein the parameter is a start magnitude.
9. The method of claim 1 , wherein the parameter is a step magnitude.
10. The method of claim 1 , wherein the parameter is a pulse width.
11. A control circuit for adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:
a memory interface configured to be operably coupled to the memory circuit; and
a controller, wherein the controller is configured to:
store a parameter, the operating condition being a function of the parameter,
monitor a memory operation for a trigger event, the trigger event including a programming time satisfying a threshold programming duration, and,
on the trigger event, adjust the parameter in accordance with a circuit characteristic associated with the memory block, and
provide to the memory interface a command representative of an instruction to apply a series of voltage pulses to a group of cells in the memory block in accordance with the adjusted parameter to adjust the operating condition.
12. The control circuit of claim 11 , wherein the operating condition includes a voltage distribution, and adjusting the operating condition includes reducing a width of an upper portion of the voltage distribution and increasing the programming time, wherein the controller being configured to adjust the parameter in accordance with the circuit characteristic includes the controller being configured to reduce the parameter.
13. The control circuit of claim 11 , wherein the operating condition includes a voltage distribution, and adjusting the operating condition includes reducing a width of a lower portion of the voltage distribution and reducing the programming time, wherein the controller being configured to adjust the parameter in accordance with a circuit characteristic includes the controller being configured to increase the parameter.
14. The control circuit of claim 11 , wherein the trigger event includes a range of P/E cycles, and wherein the controller being configured to monitor the memory operation for the trigger event includes the controller being configured to determine that a current number of PIE cycles is within the range of P/E cycles.
15. A system for adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:
a host interface configured to be operably coupled to a host device, to receive data from the host device, and to send data to the host device;
a memory interface operably coupled to the memory circuit;
a storage medium interface operably coupled to a volatile memory; and
a controller operably coupled to the host interface, wherein the controller is operable to:
store a parameter in the volatile memory, a duration of the operating condition being a function of the parameter,
monitor a memory operation for a trigger event, the trigger event including the duration of the operating condition satisfying a threshold programming duration. and,
on the trigger event, adjust the parameter in accordance with a circuit characteristic associated with the memory block, and
provide to the memory circuit a command representative of an instruction to apply a series of voltage pulses to a group of cells in the memory block in accordance with the adjusted parameter to adjust the operating condition.
16. The system of claim 15 , wherein the operating condition is a voltage distribution in the memory block, and wherein the memory circuit is configured to, in response to the command, apply the series of voltage pulses to the group of cells in the memory block in accordance with the parameter to adjust a width of the voltage distribution, each pulse in the series of pulses being an incremental step pulse such that an amplitude of each pulse is incrementally increased with each increasing pulse number, starting from a start magnitude.
17. The system of claim 15 , wherein the trigger event includes a number of P/E cycles and the circuit characteristic includes an adjustment value associated with the number of P/E cycles, wherein the controller being configured to adjust the parameter in accordance with the circuit characteristic includes the controller being configured to index a lookup table stored on the volatile memory by the number of P/E cycles to determine the adjustment value.
18. A method for adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:
storing a parameter, an erase time being a function of the parameter;
monitoring a memory operation for a trigger event, the trigger event including the erase time satisfying a threshold programming duration; and
on the trigger event, adjusting the parameter in accordance with a circuit characteristic associated with the memory block, and
providing to the memory circuit a command representative of an instruction to apply a series of voltage pulses to a group of cells in the memory block in accordance with the adjusted parameter to adjust the operating condition.
19. The method of claim 18 , wherein adjusting the operating condition includes reducing the erase time, and adjusting the parameter in accordance with a circuit characteristic includes increasing the parameter.
20. The method of claim 18 , wherein the trigger event includes the erase time reaching a minimum erase duration.
21. A control circuit for adjusting an operating condition in a memory block of a non-volatile memory circuit, comprising:
a memory interface configured to be operably coupled to the memory circuit; and
a controller, wherein the controller is configured to:
store a parameter an erase time being a function of the parameter,
monitor a memory operation for a trigger event, the trigger event including the erase time satisfying a threshold programming duration, and,
on the trigger event, adjust the parameter in accordance with a circuit characteristic associated with the memory block, and
provide to the memory interface a command representative of an instruction to apply a series of voltage pulses to a group of cells in the memory block in accordance with the adjusted parameter to adjust the operating condition.
22. The control circuit of claim 21 , wherein the operating condition includes the erase time, and adjusting the operating condition includes reducing the erase time, wherein the controller being configured to adjust the parameter in accordance with a circuit characteristic includes the controller being configured to increase the parameter.
23. The control circuit of claim 21 , wherein the trigger event includes a range of P/E cycles, and wherein the controller being configured to monitor the memory operation for the trigger event includes the controller being configured to determine that a current number of P/E cycles is within the range of P/E cycles.
24. The system of claim 15 , wherein the operating condition is a programming time, and the duration of the operating condition is a duration of the programming time.
25. The system of claim 15 , wherein the operating condition is an erase time, and the duration of the operating condition is a duration of the erase time.