IP Library Granted Patent US 9,535,870
Granted Patent B2
US 9,535,870 · App. 14/489,881 · Granted Jan 3, 2017

Acknowledgement-less protocol for solid state drive interface

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Quick Facts
Patent No.
US 9,535,870
App. No.
14/489,881
Granted
Jan 3, 2017
Kind
B2
Abstract

The present disclosure relates to methods and systems for performing operations in a communications protocol. An example method can include submitting, from a device, a request for a queue entry representing a command from a host comprising a request for data stored at a device memory location; receiving the command from the host; and executing the command. An example method can also include selecting a bit string representing whether a requested data stream has been received, and storing the bit string into a memory buffer portion to mark the buffer portion. The method can include receiving, into the memory buffer, the stream. The method can include retrieving contents of the buffer portion, and determining whether the contents contain the bit string. If so, the method can include determining that portions of the stream have not been received. Otherwise, the method can include determining that the stream has been received.

Claims (46)

1. A method of performing operations in a communications protocol, the method comprising:

selecting a bit string to indicate whether all data packets of a data request from a storage medium have been received, wherein the bit string is selected to differ from a bit sequence contained in each of the data packets of the data request;

marking a plurality of portions of a memory buffer with the selected bit string, by storing the selected bit string into the plurality of portions of the memory buffer;

receiving into the memory buffer, at least a portion of the data packets of the data request;

for each data packet that is received into one of plurality of portions of the memory buffer, overwriting the selected bit string with the bit sequence contained in the received data packet;

polling data content of the plurality of portions of the memory buffer for the selected bit string;

determining that portions of the requested data have not yet been received when the data content of any of the plurality of portions of the memory buffer contains the selected bit string; and

determining that all the requested data for the read operation has been received successfully when the data content of the plurality of portions of the memory buffer does not contain the selected bit string.

2. The method of claim 1 , wherein storing the selected bit string into the portion of the memory buffer comprises:

segmenting the memory buffer into a plurality of portions based on a size of a transaction-layer packet (TLP) in a peripheral component interconnect express (PCIe) standard, and

storing the selected bit string into the segmented plurality of portions of the memory buffer.

3. The method of claim 1 , wherein selecting the bit string comprises:

determining a size of the bit string based on a total capacity of the storage medium and on a size of an individual portion of the requested data; and

selecting a value for the bit string based on the determined size of the bit string.

4. The method of claim 3 , wherein determining the size of the bit string comprises calculating a log 2 of the total capacity of the storage medium divided by the size of the individual portion of the requested data.

5. The method of claim 3 , wherein the value for the bit string comprises a random bit sequence, wherein a length of the random bit sequence is based on the determined size of the bit string.

6. The method of claim 3 , wherein the value for the bit string is selected during an initial power-up of at least one of a host and a storage device.

7. The method of claim 3 , wherein the value for the bit string is selected upon a determination that a write operation to a storage device has invalidated a current value for the bit string.

8. The method of claim 1 , wherein the communication protocol includes commands with command formats compatible with the Non-Volatile Memory Express standard.

9. The method of claim 1 , further comprising requesting by a host in communication with the memory buffer the requested data.

10. The method of claim 9 , wherein the communication protocol is defined between the host and a target in communication with storage for storing the requested data.

11. The method of claim 10 , wherein the storage comprises at least one of a phase-change memory, magnetoresistive read only memory, and resistive read only memory.

12. A system for performing operations in a communications protocol, the system comprising:

memory in communication with a host;

a target in communication with the host via the communication protocol, for transmitting requested data for a read operation;

storage, in communication with the target, for storing and retrieving the requested data; and

a processor in communication with the host, with the memory, and with the storage, the processor configured to:

select a bit string to indicate whether all the data packets of the requested data have been received, wherein the bit string is selected to differ from a bit sequence contained in each of the data packets of the requested data;

mark a plurality of portions of the memory buffer with the selected bit string, by storing the selected bit string into each of the plurality of portions of the memory buffer;

receive into the memory buffer, at least a portion of the data packets of the requested data;

for each data packet that is received into one of plurality of portions of the memory buffer, overwrite the selected bit string with the bit sequence contained in the received data packet;

poll data content of the plurality of portions of the memory buffer for the selected bit string;

determine that portions of the requested data have not yet been received when the data content of any of the plurality of portions of the memory buffer contains the selected bit string; and

determine that all the requested data for the read operation has been received successfully when the data content of the plurality of portions of the memory buffer does not contain the selected bit string.

13. The system of claim 12 , wherein processor configured to store the selected bit string into the portion of the memory buffer comprises the processor being configured to:

segment the memory buffer into a plurality of portions, wherein a size of each portion is based on a size of a transaction-layer packet (TLP) in a peripheral component interconnect express (PCIe) standard; and

store the selected bit string into the segmented plurality of portions of the memory buffer.

14. The system of claim 12 , wherein the processor configured to select the bit string comprises the processor being configured to:

determine a size of the bit string based on a total capacity of the storage medium and on a size of an individual portion of the requested data; and

select a value for the bit string based on the determined size of the bit string.

15. The system of claim 14 , wherein processor configured to determine the size of the bit string comprises the processor being configured to calculate a log 2 of the total capacity of the storage medium divided by the size of the individual portion of the requested data.

16. The system of claim 14 , wherein the value for the bit string comprises a random bit sequence, wherein a length of the random bit sequence is based on the determined size of the bit string.

17. The system of claim 14 , wherein the value for the bit string is selected during an initial power-up of at least one of a host and a storage device.

18. The system of claim 14 , wherein the value for the bit string is selected upon a determination that a write operation to a storage device has invalidated a current value for the bit string.

19. The system of claim 12 , wherein the communication protocol includes commands with command formats compatible with the Non-Volatile Memory Express standard.

20. The system of claim 12 , wherein the storage comprises at least one of a phase-change memory, magnetoresistive read only memory, and resistive read only memory.

Assignments (11)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040829/0516 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 31, 2014
From: BANDIC, ZVONIMIR Z.; CHU, FRANK R.; GUYOT, CYRIL; MATEESCU, ROBERT; VUCINIC, DEJAN; WANG, QINGBO
To: HGST NETHERLANDS B.V.
Reel/Frame 034080/0760 →