Read disturb compensation using weighted programming patterns
A data storage device includes a solid-state non-volatile memory including a plurality of memory cells and a controller. The controller is configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by receiving or accessing data to be written to the solid-state non-volatile memory, encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher voltage level than the second programming state, and writing the encoded data to the solid-state non-volatile memory.
1. A data storage device comprising:
a solid-state non-volatile memory including a plurality of memory cells; and
a controller configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by:
receiving or accessing data to be written to the solid-state non-volatile memory;
encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher voltage level than the second programming state; and
writing the encoded data to the solid-state non-volatile memory.
2. The data storage device of claim 1 , further comprising a data randomizer, wherein the controller is further configured to turn off the data randomizer.
3. The data storage device of claim 1 , wherein the controller is further configured to:
determine that a read disturb programming mode is set; and
perform said encoding the data using the programming pattern in response to said determination that the read disturb programming mode is set.
4. The data storage device of claim 1 , wherein the controller is further configured to utilize a weighted algorithm when encoding the data using the programming pattern.
5. The data storage device of claim 1 , wherein the data to be written is internal system data.
6. The data storage device of claim 1 , wherein the controller is further configured to perform said encoding the data using the programming pattern in response to a condition indicating that read disturb compensation is to be implemented.
7. The data storage device of claim 6 , wherein the condition corresponds to receipt of a host command to program the data using the programming pattern.
8. The data storage device of claim 6 , wherein the condition corresponds to detection of a program/erase cycle preceding high-read utilization of a block of the solid-state non-volatile memory.
9. The data storage device of claim 1 , wherein:
the controller is further configured to perform said accessing the data at least in part by reading the data from the solid-state non-volatile memory; and
when read from the solid-state non-volatile memory, the data is programmed according to a randomized programming pattern.
10. The data storage device of claim 1 , wherein second programming state corresponds to a lowest programming state of a multiple-state programming scheme.
11. The data storage device of claim 1 , wherein the programming pattern further favors a third programming state over the first programming state, the third programming state being associated with a higher voltage level than the first programming state.
12. A data storage device comprising:
a solid-state non-volatile memory including a plurality of memory cells; and
a controller configured to improve data retention of at least a portion of the solid-state non-volatile memory at least in part by:
reading data stored in the solid-state non-volatile memory according to a randomized programming pattern;
reencoding the data using a programming pattern that favors a first programming state over a second programming state; and
reprogramming the encoded data to the solid-state non-volatile memory.
13. The data storage device of claim 12 , wherein the first programming state is associated with a higher voltage level than the second programming state.
14. The data storage device of claim 12 , wherein the first programming state is associated with a lower voltage level than the second programming state.
15. The data storage device of claim 12 , wherein the controller is further configured to perform said reading, reencoding, and reprogramming in response to a determination that a weighted programming mode is set.
16. The data storage device of claim 15 , wherein said determination that the weighted programming mode is set is based on a flag that indicates that the weighted programming mode is set.
17. The data storage device of claim 12 , wherein the controller is further configured to perform said reading, reencoding, and reprogramming in anticipation of a power-down of the data storage device.
18. A data storage device comprising:
a solid-state non-volatile memory including a plurality of memory cells;
means for encoding data using a weighted programming pattern that favors a first programming state of a second programming state, the first programming state being associated with a higher voltage level than the second programming state; and
controller circuitry configured to reduce a read disturb effect of at least a portion of the solid-state non-volatile memory at least in part by:
receiving or accessing data to be written to the solid-state non-volatile memory;
encoding the data according to the weighted programming pattern using the means for encoding data; and
writing the encoded data to the solid-state non-volatile memory.
19. The data storage device of claim 18 , further comprising:
a data randomizer; and
means for bypassing the data randomizer.
20. A method of programming data, the method comprising:
receiving or accessing data to be written to a solid-state non-volatile memory;
determining that a read disturb compensation programming mode associated with the solid-state non-volatile memory is set; and
in response to said determination:
encoding the data using a programming pattern that favors a first programming state over a second programming state, the first programming state being associated with a higher programming voltage level than the second programming state; and
writing the encoded data to the solid-state non-volatile memory.
21. The method of claim 20 , further comprising bypassing a data randomizer in response to the determination that the read disturb compensation programming mode is set.
22. The method of claim 20 , further comprising receiving a request to set the read disturb compensation programming mode from a host device communicatively coupled to a data storage device over an interface, the data storage device comprising the solid-state non-volatile memory.
23. The method of claim 20 , wherein said determining that the read disturb compensation programming mode is set is based on a type of the data.
24. The method of claim 20 , wherein the programming pattern further favors a third programming state over the first programming state, the third programming state being associated with a higher voltage level than the first programming state.
25. A data storage device comprising:
a solid-state non-volatile memory including a plurality of memory cells; and
a controller configured to reduce bit error rate for at least a portion of the solid-state non-volatile memory at least in part by:
accessing data to be written to the solid-state non-volatile memory;
determining that a weighted programming mode is set; and
in response to said determining that the weighted programming mode is set:
encoding the data using a programming pattern that favors a first programming state over a second programming state; and
writing the encoded data to the solid-state non-volatile memory.
26. The data storage device of claim 25 , wherein the first programming state is associated with a higher voltage level than the second programming state.
27. The data storage device of claim 25 , wherein the first programming state is associated with a lower voltage level than the second programming state.