IP Library Granted Patent US 11,829,647
Granted Patent B1
US 11,829,647 · App. 17/828,285 · Granted Nov 28, 2023

Storage system and method for using a queue monitor in a block allocation process

Inventors: Kalpit Bordia (Karnataka, IN); Disha Gundecha (Maharashtra, IN); Raviraj Raju (Karnataka, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 11,829,647
App. No.
17/828,285
Granted
Nov 28, 2023
Kind
B1
Abstract

A storage system has a memory with a multi-level cell (MLC) block that can store multiple bits per cell or can be constrained to store only one bit per cell. Using the MLC block to store only one bit per cell can increase the performance of the storage system but can also reduce endurance of the MLC block. The storage system can monitor a command queue to determine the performance needed. With that information, the storage system can determine whether it is worth making the tradeoff of increasing performance at the cost of endurance.

Claims (31)

1. A storage system comprising:

a memory comprising a multi-level cell (MLC) block; and

a controller coupled with the memory and configured to:

analyze commands in a command queue to determine a performance requirement;

determine whether the performance requirement will be satisfied if the MLC block is allocated as a dedicated MLC block that stores multiple bits per memory cell;

in response to determining that the performance requirement will be satisfied, allocating the MLC block as a dedicated MLC block; and

in response to determining that the performance requirement will not be satisfied, allocating the MLC block as a hybrid single-level cell (hSLC) block that stores only a single bit per memory cell.

2. The storage system of claim 1 , wherein the controller is further configured to determine the performance requirement based on a rate at which a host schedules commands in the command queue.

3. The storage system of claim 1 , wherein the controller is further configured to determine the performance requirement based on a latency in a read and/or write path in the storage system.

4. The storage system of claim 1 , wherein the controller is further configured to determine the performance requirement based on whether the command queue comprises one or more of the following: a forced unit access (FUA) command, a trim command, an administrative command, an unaligned write command, a security command, or a vendor-specific command.

5. The storage system of claim 1 , wherein the controller is further configured to determine the performance requirement based on a thermal condition of the storage system.

6. The storage system of claim 1 , wherein the controller is further configured to determine a ratio of dedicated MLC blocks and hSLC blocks.

7. The storage system of claim 1 , wherein the controller is further configured to place the storage system in a delayed hybrid allocation state.

8. The storage system of claim 1 , wherein the controller is further configured to analyze commands in the command queue to determine whether to perform an age-based relocation process.

9. The storage system of claim 1 , wherein the controller is further configured to perform a folding operation to help satisfy the performance requirement.

10. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

11. In a storage system comprising a memory comprising a multi-level cell (MLC) block, a method comprising:

monitoring a command queue;

receiving an allocation request; and

based on the monitoring of the command queue, determining whether to allocate the MLC block as a dedicated MLC block that stores multiple bits per memory cell or as a hybrid single-level cell (hSLC) block that stores only a single bit per memory cell.

12. The method of claim 11 , wherein the determining is based on fullness of the memory.

13. The method of claim 11 , wherein the determining is based on endurance of the memory.

14. The method of claim 11 , wherein the determining is based on a needed write bandwidth.

15. The method of claim 11 , wherein the determining is based on whether the command queue comprises one or more of the following: a forced unit access (FUA) command, a trim command, an administrative command, an unaligned write command, a security command, or a vendor-specific command.

16. The method of claim 11 , further comprising performing a thermal management operation based on the monitoring.

17. The method of claim 11 , further comprising performing a foreground relocation operation based on the monitoring.

18. The method of claim 11 , wherein the memory comprises a three-dimensional memory.

19. A storage system comprising:

a memory comprising a multi-level cell (MLC) block;

means for monitoring a command queue to determine a required bandwidth; and

means for using the MLC block to store multiple bits per memory cell in response to such use providing the required bandwidth; otherwise, using the MLC block to store only one bit per memory cell.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 31, 2022
From: BORDIA, KALPIT; GUNDECHA, DISHA; RAJU, RAVIRAJ
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060056/0864 →