IP Library Granted Patent US 10,235,309
Granted Patent B1
US 10,235,309 · App. 15/824,658 · Granted Mar 19, 2019

Combined control for multi-die flash

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Quick Facts
Patent No.
US 10,235,309
App. No.
15/824,658
Granted
Mar 19, 2019
Kind
B1
Abstract

A method, having steps of monitoring a bus for a change in an aggregated ready/busy indicator from a busy status to a ready status, the change in the aggregated ready/busy indicator to the ready status indicating at least one die is ready to perform a computer function, scheduling at least one logic queue with a next command to the ready die when the aggregated ready/busy indicator is in a ready status and setting the aggregated ready/busy indicator to a busy status after the scheduling of the at least one logic queue.

Claims (49)

1. A method, comprising:

monitoring a bus for a change in an aggregated ready/busy indicator from a busy status to a ready status, the change in the aggregated ready/busy indicator to the ready status indicating at least one die is ready to perform a computer function;

scheduling at least one logic queue with a next command to the ready die when the aggregated ready/busy indicator is in a ready status;

transmitting the next command to all of the dies;

setting the aggregated ready/busy indicator to a busy status after the scheduling of the at least one logic queue and transmitting the next command to all of the dies through a chip enable signal;

receiving the next command at all of the dies; and

performing the next command at one of the dies.

2. The method according to claim 1 , further comprising:

deducing a die number from the monitoring of the bus.

3. The method according to claim 1 , wherein the bus is a common bus.

4. The method according to claim 1 , further comprising performing the computer function at the ready die.

5. The method according to claim 4 , further comprising:

resuming the monitoring of the bus.

6. The method according to claim 1 , wherein the monitoring of the bus is through a controller.

7. A method, comprising:

determining a die ready for performing a command;

scheduling at least one logic queue with the command to the ready die when an aggregated ready/busy indicator is in a ready status;

turning on a combined chip enable signal, the combined chip enable signal indicating a die number for selection of the command;

transmitting the command;

receiving the command at the die number selected; and

performing the command at the die number selected.

8. The method according to claim 7 , wherein the transmitting the command is performed on a computer bus.

9. The method according to claim 7 , wherein a computer bus is a common computer bus.

10. The method according to claim 7 , further comprising:

turning off the combined chip enable signal after the performing of the command at the die number selected.

11. The method according to claim 7 , further comprising:

determining a second die ready to perform a second command.

12. The method according to claim 11 , further comprising:

turning on the combined chip enable signal, the combined chip enable signal indicating a second die number for selection of a next command;

transmitting the next command;

receiving the next command at the die number selected; and

performing next command at the die number selected.

13. An arrangement, comprising:

means for monitoring a bus for a change in an aggregated ready/busy indicator from a busy status to a ready status, the change in the aggregated ready/busy indicator to the ready status indicating at least one die is ready to perform a computer function;

means for scheduling at least one logic queue with a next command to the ready die when the aggregated ready/busy indicator is in a ready status;

means for setting the aggregated ready/busy indicator to a busy status after the scheduling of the at least one logic queue and transmitting the next command to all of the dies through a chip enable signal; and

means for receiving the next command at all of the dies.

14. A method, comprising:

monitoring a bus for a change in an aggregated ready/busy indicator from a busy status to a ready status for at least one die, the change in the aggregated ready/busy indicator to the ready status indicating at least one die is ready to perform a computer function;

scheduling at least one logic queue with a next command to the ready die when the aggregated ready/busy indicator is in a ready status;

transmitting the next command to all of the dies through a chip enable signal;

setting the ready/busy indicator for at least one die to a busy status after the scheduling of the at least one logic queue;

setting the aggregated ready/busy indicator to a busy indication which reflects a status of all dies; and

monitoring the bus for a second change in an aggregated ready/busy indicator from the busy status to the ready status, wherein the change in the aggregated ready/busy indicator to the ready status indicates at least one die is ready to perform a second computer function.

15. The method according to claim 14 , further comprising:

deducing a die number from the monitoring of the bus.

16. The method according to claim 14 , wherein the bus is a common bus.

17. The method according to claim 14 , further comprising performing the computer function at the ready die.

18. The method according to claim 17 , where the computer function is at least one of a write, read and erase function for a data storage arrangement.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2018
From: MARKUS, YOAV; BAZARSKY, ALEXANDER
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 044833/0123 →