Methods and systems for implementing redundancy in memory controllers
View Patent ↗The present disclosure relates to methods and systems for implementing redundancy in memory controllers. The disclosed systems and methods utilize a row of memory blocks, such that each memory block in the row is associated with an independent media unit. Failures of the media units are not correlated, and therefore, a failure in one unit does not affect the data stored in the other units. Parity information associated with the data stored in the memory blocks is stored in a separate memory block. If the data in a single memory block has been corrupted, the data stored in the remaining memory blocks and the parity information is used to retrieve the corrupted data.
1. A method for introducing redundancy in a memory controller, the method comprising:
initializing, by the memory controller, a plurality of data memory elements to a logical zero value, each data memory element being associated with a corresponding non-volatile storage element, the plurality of data memory elements including a parity data memory element;
receiving, from a host computer, a first data block associated with a first data memory element;
storing, by the memory controller, to the first data memory element a first result of a logical operation between a value in the first data block and a value in the first data memory element;
storing, by the memory controller, to the parity data memory element a second result of a logical operation between the value in the first data block and the value in the parity data memory element;
receiving, from the host computer, a second data block associated with a second data memory element;
storing, by the memory controller, to the second data memory element a third result of a logical operation between a value in the second data block and a value in the second data memory element;
storing, by the memory controller, to the parity data memory element a fourth result of a logical operation between the value in the second data block and the value in the parity data memory element.
2. The method of claim 1 , further comprising:
transferring, by the memory controller, the stored data from the data memory elements to their corresponding non-volatile storage elements; and
initializing, by the memory controller, the data memory elements to a logical zero, after transferring the stored data from the data memory elements to the first non-volatile storage elements.
3. The method of claim 1 , wherein the logical operations are exclusive OR logical operations.
4. The method of claim 3 , wherein a value in the parity data memory element is stored incrementally.
5. The method of claim 3 , wherein a value stored in a first data memory element can be restored from the values of the data memory elements in a valid state and a value of the parity data memory element.
6. The method of claim 1 , wherein each corresponding non-volatile storage element is located in an independent media unit.
7. A memory controller comprising:
a plurality of data memory elements, each data memory element being associated with a corresponding non-volatile storage element, the plurality of data memory elements including a parity data memory element; and
a controller module configured to:
initialize the plurality of data memory elements to a logical zero value;
receive, from a host computer, a first data block associated with a first data memory element;
store to the first data memory element a first result of a logical operation between a value in the first data block and a value in the first data memory element;
store to the parity data memory element a second result of a logical operation between the value in the first data block and the value in the parity data memory element;
receive, from the host computer, a second data block associated with a second data memory element;
store, by the memory controller, to the second data memory element a third result of a logical operation between a value in the second data block and a value in the second data memory element;
store, by the memory controller, to the parity data memory element a fourth result of a logical operation between the value in the second data block and the value in the parity data memory element.
8. The memory controller of claim 7 , wherein the controller module is further configured to:
transfer the stored data from the data memory elements to their corresponding non-volatile storage elements; and
initialize the data memory elements to a logical zero, after transferring the stored data from the data memory elements to the first non-volatile storage elements.
9. The memory controller of claim 7 , wherein the logical operations are exclusive OR logical operations.
10. The memory controller of claim 9 , wherein a value in the parity data memory element is stored incrementally.
11. The memory controller of claim 9 , wherein a value stored in a first data memory element can be restored from the values of the data memory elements in a valid state and a value of the parity data memory element.
12. The memory controller of claim 7 , wherein each corresponding non-volatile storage element is located in an independent media unit.