IP Library Granted Patent US 10,949,119
Granted Patent B2
US 10,949,119 · App. 15/900,531 · Granted Mar 16, 2021

Data shaping to reduce error rates in solid state memory devices

Inventors: David Rozman (Kiryat-Malakhi, IL); Stella Achtenberg (Netanya, IL); Arthur Shulkin (Yavne, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0619G06F3/0679G06F11/076G06F11/0727G11C7/1006G11C16/10G11C16/26G11C16/3495G11C11/5628G11C11/5642G11C11/5671G11C16/0483
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Quick Facts
Patent No.
US 10,949,119
App. No.
15/900,531
Granted
Mar 16, 2021
Kind
B2
Abstract

Systems and methods are described for reducing error rates on data storage devices by applying data shaping to data written to such devices in order to avoid error-prone states on cells within the devices. Different states of individual cells (such as those representing different bit patterns) may have different propensities for error, and these propensities may vary during operation of a device. Thus, a device as disclosed herein may determine error-prone states for a cell or group of cells, and apply data shaping to data written to such cells to reduce the likelihood that writing the data places the cell or cells into an error-prone state. Data shaping may be used, for example, to increase the occurrence of “0” bits within input data, thus avoiding error-prone low voltage states that may be used to represent a series of “1” bits.

Claims (60)

1. A memory device comprising:

a non-volatile memory comprising non-volatile solid-state memory cells, the cells arranged into a plurality of blocks; and

a controller comprising a processor and configured to:

prior to determining a data shaping to be applied to input data:

obtain, for a first block of the plurality of blocks, information reflective of measured characteristics of the first block by performing write and read operations to the first block, wherein the measured characteristics vary among the plurality of blocks, the information identifying an expected voltage range for each state of a plurality of states in which non-volatile solid-state memory cells of the first block may be placed; and

identify a state, of the plurality of states, whose expected voltage range overlaps with the expected voltage range of another state of the plurality of states, wherein the state is representative of a data value;

determine, based at least partly on the state, the data shaping to be applied to the input data intended to be written to the first block, wherein the data shaping transforms the input data into an output data while reducing a probability of the data value occurring within the output data relative to a probability of the data value occurring within the input data;

receive the input data;

apply the data shaping to the input data to transform the input data into the output data; and

write the output data to the block, wherein the input data, if written to the first block, would result in the non-volatile solid-state memory cells of the first block being placed in a uniform distribution of the plurality of states, and wherein the output data, when written to the block, results in the non-volatile solid-state memory cells of the first block being placed in a non-uniform distribution of the plurality of states.

2. The memory device of claim 1 , wherein the non-volatile memory includes at least one of single-level cell (SLC) memory, 2-bits per cell multi-level cell (MLC) memory, 3-bits per cell MLC memory, of 4-bits per cell MLC memory.

3. The memory device of claim 1 , wherein the controller is further configured to:

receive a request to read the first block;

read the output data from the first block;

apply an inversion of the data shaping to the output data to transform the output data into the input data; and

respond to the request by providing the input data.

4. The memory device of claim 1 , wherein the controller is configured to obtain the information identifying the expected voltage range for each state of the plurality of states in which the first block may be placed based at least partly on conducting read/write operations on the first block.

5. The memory device of claim 1 , wherein the information identifying the expected voltage range for each state of the plurality of states in which the first block may be placed is represented as a voltage distribution for the first block, and wherein the controller is configured to obtain the voltage distribution for the first block based at least partly on comparing characteristics of the first block to information mapping the characteristics to the voltage distribution.

6. The memory device of claim 1 , wherein the controller is configured to identify the first block based at least partly on detecting that an error rate of the first block meets a threshold rate.

7. The memory device of claim 1 , wherein the non-volatile memory stores a plurality of data shapings each associated with a reduction in use of a corresponding state, and wherein the controller is configured to determine the data shaping to be applied to the input data at least partly by selecting the data shaping from the plurality of data shapings according to the identified state.

8. The memory device of claim 1 , wherein the non-volatile memory stores a data shaping algorithm associated with parameters, and wherein the controller is configured to determine the data shaping by setting the parameters of the data shaping algorithm.

9. The memory device of claim 8 , wherein the parameters of the data shaping algorithm include a probability of one or more bit values within the data value occurring within the output data.

10. The memory device of claim 8 , wherein the parameters of the data shaping algorithm include relative preference for the data value within the output data relative to other potential data values.

11. The memory device of claim 8 , wherein the controller is configured to set the parameters of the data shaping algorithm based at least partly on an overlap between the expected voltage range of the identified state with the expected voltage range of the other state.

12. The memory device of claim 1 , wherein the state represents a lowest voltage range state relative to other states of the plurality of states.

13. The memory device of claim 1 , wherein the state represents a highest voltage range state relative to other states of the plurality of states.

14. A method implemented on a memory device, the method comprising:

prior to applying a data shaping to input data:

obtaining, for a group of cells on the memory device, information reflective of measured characteristics of the group of cells by performing write and read operations to the group of cells, wherein the measured characteristics vary among groups of cells on the memory device, the information identifying expected voltage ranges for at least two states in which individual cells within the group of cells may be placed; and

identifying a state, of the at least two states, whose expected voltage range overlaps with the expected voltage range of another state of the at least two states, wherein the state is representative of a data value;

obtaining the input data to be written to the group of cells;

applying the data shaping to the input data to generate output data, wherein the data shaping is selected at least partly based on the identified state, and wherein the data shaping transforms the input data into the output data while reducing a probability of the data value occurring within the output data relative to a probability of the data value occurring within the input data; and

storing the output data within the group of cells.

15. The method of claim 14 , wherein obtaining the information identifying the expected voltage ranges for the at least two states in which the group of cells may be placed comprises conducting read/write operations on the group of cells.

16. The method of claim 14 , wherein the information identifying the expected voltage ranges for the at least two states in which the group of cells may be placed is represented as a voltage distribution for the group of cells, and wherein obtaining the voltage distribution for the group of cells comprises comparing characteristics of the group of cells to information mapping the characteristics to the voltage distribution.

17. The method of claim 14 further comprising identifying the group of cells based at least partly on detecting that an error rate of the group of cells meets a threshold rate.

18. The method of claim 14 , wherein the data shaping is selected from a plurality of data shapings based at least partly on the identified state.

19. The method of claim 14 , wherein the data shaping is selected at least partly by setting parameters of a data shaping algorithm according to the identified state.

20. The method of claim 14 , wherein the input data, if written to the group of cells, results in the group of cells being placed in a uniform distribution between the at least two states, and wherein the output data, when written to the group of cells, results in the group of cells being placed in a non-uniform distribution between the at least two states.

21. The method of claim 14 , wherein the state represents a lowest voltage range state relative to other states of the at least two states.

22. The method of claim 19 , wherein the parameters of the data shaping algorithm are further set according to an overlap between the expected voltage range of the identified state with the expected voltage range of the other state.

23. A memory device comprising:

a non-volatile memory; and

a controller comprising a processor and configured to:

prior to applying a data shaping to input data:

obtain, for a group of cells of the non-volatile memory, information reflective of measured characteristics of the group of cells by performing write and read operations to the group of cells, wherein the measured characteristics vary among groups of cells on the memory, the information identifying expected voltage ranges for at least two states in which the group of cells may be placed; and

identify a state, of the at least two states, whose expected voltage range overlaps with the expected voltage range of another state of the at least two states, wherein the state is representative of a data value;

obtain the input data to be written to the group of cells;

apply the data shaping to the input data to generate output data, wherein the data shaping is selected at least partly based on the identified state, and wherein the data shaping transforms the input data into the output data while reducing a probability of the data value occurring within the output data relative to a probability of the data value occurring within the input data; and

store the output data within the group of cells.

24. A memory device, comprising:

means for storing a plurality of blocks of data; and

controller means coupled to the means for storing, wherein the controller means is configured to:

receive input data;

prior to determining a data shaping to be applied to the input data:

obtain, for a first block of the plurality of blocks, information reflective of measured characteristics of the first block by performing write and read operations to the first block, wherein the measured characteristics vary among the plurality of blocks, the information identifying an expected voltage range for each state of a plurality of states in which non-volatile solid-state memory cells of the first block are placed; and

identify a state, of the plurality of states, whose expected voltage range overlaps with the expected voltage range of another state of the plurality of states, wherein the state is representative of a data value;

determine, based at least partly on the state, the data shaping to be applied to the input data intended to be written to the first block, wherein the data shaping transforms the input data into output data while reducing a probability of the data value occurring within the output data relative to a probability of the data value occurring within the input data;

apply the data shaping to the input data to transform the input data into the output data; and

write the output data to the block, wherein the input data, if written to the first block, results in the non-volatile solid-state memory cells of the first block being placed in a uniform distribution of the plurality of states, and wherein the output data, when written to the block, results in the non-volatile solid-state memory cells of the first block being placed in a non-uniform distribution of the plurality of states.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 27, 2018
From: ROZMAN, DAVID; ACHTENBERG, STELLA; SHULKIN, ARTHUR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046999/0349 →
Continuity (1)
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