Storage device for performing a state shaping operation on data based on a speed characteristic of a memory cell and operation method thereof
A storage device according to an embodiment includes a memory device configured to apply a first program voltage and a first verification voltage to a first word line and output, based on a program state of each of a plurality of memory cells connected to the first word line, a speed information representing a speed characteristic of each of the plurality of memory cells; and a memory controller configured to determine at least one memory cell to be programmed into a predetermined program state; determine, among the at least one memory cell, at least one target memory cell having a first speed characteristic based on the speed information; and perform a state-shaping operation to convert a data corresponding to the predetermined program state for the at least one target memory cell into a value corresponding to a program state different from the predetermined program state.
1 . A storage device comprising:
a memory device configured to select a first word line among a plurality of word lines; apply a first program voltage and a first verification voltage to the first word line; and output, based on a program state of each of a plurality of memory cells connected to the first word line that is read based on the first verification voltage, a speed information representing a speed characteristic of each of the plurality of memory cells; and
a memory controller configured to determine, among the plurality of memory cells, at least one memory cell to be programmed into a predetermined program state among a plurality of program states; determine, among the at least one memory cell, at least one target memory cell having a first speed characteristic based on the speed information; and perform a state-shaping operation to convert a data corresponding to the predetermined program state for the at least one target memory cell into a value corresponding to a program state that is different from the predetermined program state,
wherein the memory controller is configured to, based on a number of memory cells to be programmed into the predetermined program state and having the first speed characteristic exceeding a predetermined number, determine, among the number of memory cells, the at least one target memory cell of the predetermined number or less.
2 . The storage device of claim 1 , wherein the memory controller is configured to perform the state-shaping operation to convert the data corresponding to the predetermined program state into a value corresponding to a lower program state than the predetermined program state.
3 . The storage device of claim 2 , wherein the predetermined program state is a higher program state than a reference program state, and the lower program state is a program state lower than the reference program state, the reference program state being determined according to an external input or a predetermined reference.
4 . The storage device of claim 1 , wherein the predetermined program state includes a plurality of predetermined program states, and a number of a target memory cell in a higher program state among the plurality of predetermined program states is greater than a number of a target memory cell in a lower program state among the plurality of predetermined program states.
5 . The storage device of claim 1 , wherein the predetermined program state is a highest program state among the plurality of program states.
6 . The storage device of claim 2 , wherein the plurality of program states includes a plurality of lower program states than the predetermined program state, and
wherein a number of memory cells having the first speed characteristic and programmed into each of the plurality of lower program states increases equally according to the state-shaping operation.
7 . The storage device of claim 2 , wherein the plurality of program states includes a plurality of lower program states than the predetermined program state, and
wherein a number of memory cells having the first speed characteristic and programmed into each of the plurality of lower program states increases randomly according to the state-shaping operation.
8 . The storage device of claim 1 , wherein based on the first program voltage being applied to the first word line, the at least one target memory cell has a threshold voltage equal to or higher than the first verification voltage.
9 . The storage device of claim 1 , wherein the memory controller is configured to not perform the state-shaping operation for a memory cell, among the plurality of memory cells, of which a speed characteristic is different from the first speed characteristic.
10 . An operation method of a storage device comprising:
selecting a first word line among a plurality of word lines;
generating a speed information representing a speed characteristic of each of a plurality of memory cells connected to the first word line;
determining at least one memory cell among the plurality of memory cells that is programmed into a predetermined program state among a plurality of program states;
determining a first memory cell having a first speed characteristic among the at least one memory cell, based on the speed information; and
performing a state-shaping operation to convert a data corresponding to the predetermined program state for the first memory cell into a value corresponding to a program state different from the predetermined program state,
wherein the determining the first memory cell comprises, based on a number of memory cells to be programmed into the predetermined program state and having the first speed characteristic exceeding a predetermined number, determining, among the number of memory cells, the first memory cell of the predetermined number or less.
11 . The operation method of the storage device of claim 10 , wherein the generating the speed information includes:
applying a first program voltage and a first verification voltage to the first word line; and
reading a program state of each of the plurality of memory cells based on the first verification voltage, and generating the speed information based on the read program state.
12 . The operation method of the storage device of claim 10 , wherein the first memory cell has a higher threshold voltage among the at least one memory cell.
13 . The operation method of the storage device of claim 10 , wherein the performing the state-shaping operation includes:
generating a state-shaped data having a value corresponding to a lower program state than the predetermined program state.
14 . The operation method of the storage device of claim 13 , wherein the predetermined program state is a higher program state than a reference program state, and the lower program state is a program state lower than the reference program state, the reference program state being determined according to an external input or a predetermined reference.
15 . The operation method of the storage device of claim 13 , wherein the predetermined program state is a highest program state among the plurality of program states.
16 . The operation method of the storage device of claim 13 , further comprising:
inversely transforming the state-shaped data; and
transmitting data generated through the inversely transforming the state-shaped data to an outside of a memory controller of the storage device.
17 . A computing system comprising:
a host device configured to output a command requesting a program operation of a memory device; and
a memory controller configured to receive, from the memory device, a speed information indicating whether a plurality of memory cells connected to a select word line are fast cells or slow cells; determine a target memory cell, among the fast cells, that is to be programmed into a predetermined program state among a plurality of program states; and perform, based on the command, a state-shaping operation on a data corresponding to the predetermined program state for the target memory cell,
wherein the memory controller is configured to, based on a number of fast cells to be programmed into the predetermined program state exceeding a predetermined number, determine, among the number of fast cells, the target memory cell of the predetermined number or less.
18 . The computing system of claim 17 , wherein the speed information is received from the memory device based on a first program loop on the select word line, the speed information being based on a program state of each of the plurality of memory cells that is read based on the first program loop.
19 . The computing system of claim 17 , wherein the predetermined program state is a higher program state than a reference program state that is determined according to an external input or a predetermined reference, or the predetermined program state is a highest program state among the plurality of program states.