IP Library Granted Patent US 11,663,136
Granted Patent B2
US 11,663,136 · App. 16/910,973 · Granted May 30, 2023

Storage capacity recovery source selection

Inventors: Hongmei Xie (Milpitas, CA); Dhanunjaya Rao Gorrle (Milpitas, CA); Aajna Karki (San Jose, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/10G06F12/0253G06F2212/1044
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Quick Facts
Patent No.
US 11,663,136
App. No.
16/910,973
Granted
May 30, 2023
Kind
B2
Abstract

A non-volatile memory device includes a volatile memory, a non-volatile memory, and a controller. The controller is configured to map logical addresses for stored data to physical addresses of the stored data in the non-volatile memory using a logical-to-physical mapping structure stored partially in the volatile memory and at least partially in the non-volatile memory. The controller is configured to perform a storage capacity recovery operation for a region of the non-volatile memory that is selected based at least partially on a number of mappings for the region likely to be stored in the volatile memory for the storage capacity recovery operation.

Claims (35)

1. A system comprising:

a non-volatile memory device comprising:

volatile memory;

a non-volatile memory; and

a controller, wherein the controller is configured to:

map logical addresses for stored data to physical addresses of the stored data in the non-volatile memory using a logical-to-physical mapping structure stored partially in the volatile memory and at least partially in the non-volatile memory; and

perform a storage capacity recovery operation for a region of the non-volatile memory, the region selected based on the region having a lowest amount of valid data out of a group of regions selected as having both less than a threshold amount of valid data and more than a threshold number of mappings that are estimated to be stored in the volatile memory for the storage capacity recovery operation, the estimate determined based on a tracked hit count and a tracked valid data count for the selected region.

2. The system of claim 1 , wherein the number of mappings for the region that are estimated to be stored in the volatile memory for the storage capacity recovery operation is determined on a per-command basis as data is written to the region.

3. The system of claim 2 , wherein the per-command determination for a command is based on a number of logical addresses written by the command and on a number of logical address mappings stored per page of the logical-to-physical mapping structure.

4. The system of claim 1 , wherein the storage capacity recovery operation for the region comprises writing valid data from the region to a different region and erasing the region.

5. The system of claim 4 , wherein the controller is further configured to determine the valid data from the region based on entries in the logical-to-physical mapping structure such that performing the storage capacity recovery operation for the region is faster than performing a storage capacity recovery operation on another region with a lower number of mappings estimated to be stored in the volatile memory than the region.

6. The system of claim 4 , wherein the region is further selected based partially on a size of the valid data from the region.

7. The system of claim 6 , wherein the region is selected for the storage capacity recovery operation in response to the region having a highest number of mappings estimated to be stored in the volatile memory for the storage capacity recovery operation out of regions having a lowest amount of valid data.

8. The system of claim 6 , wherein the region is selected for the storage capacity recovery operation in response to the region having a highest number of mappings estimated to be stored in the volatile memory for the storage capacity recovery operation out of a group of regions selected as having both less than a threshold amount of valid data and more than a threshold number of mappings estimated to be stored in the volatile memory for the storage capacity recovery operation.

9. The system of claim 6 , wherein the region is selected for the storage capacity recovery operation in response to the region having a highest number of mappings estimated to be stored in the volatile memory for the storage capacity recovery operation out of a largest group of regions having an amount of valid data within a predetermined valid data range of each other.

10. The system of claim 4 , wherein the storage capacity recovery operation for the region further comprises writing invalid data from the region to the different region with the valid data.

11. The system of claim 10 , wherein the region is selected for the storage capacity recovery operation in response to the region being a least frequently used region and the different region comprises a most frequently used region.

12. The system of claim 10 , wherein the invalid data is written with the valid data in response to a plurality of regions of the non-volatile memory having an amount of valid data above a threshold and a number of mappings estimated to be stored in the volatile memory for the storage capacity recovery operation below a threshold.

13. An apparatus comprising:

a mapping module configured to map logical addresses for stored data to physical addresses of the stored data in a non-volatile memory using a logical-to-physical mapping structure stored partially in volatile memory and at least partially in the non-volatile memory;

a hit count module configured to track, per block of the non-volatile memory, a hit count and a valid data count that are used to estimate a number of mappings of the logical-to-physical mapping structure estimated to be stored in the volatile memory for a garbage collection operation and indicate an amount of valid data in a region of the volatile memory; and

a garbage collection module configured to perform a garbage collection operation for one of the blocks of the non-volatile memory that is selected in response to having a lowest amount of valid data out of a group of blocks selected as having both a valid count that is less than a threshold amount of valid data and a hit count that is more than a threshold number of mappings estimated to be stored in the volatile memory for the garbage collection operation.

14. The apparatus of claim 13 , wherein the garbage collection operation comprises writing valid data from the block to a different block and erasing the block, and the garbage collection module is further configured to determine the valid data from the block based on entries in the logical-to-physical mapping structure such that performing the garbage collection operation for the block is faster than performing a garbage collection operation on another block with a lower hit count than the block.

15. The apparatus of claim 13 , wherein the garbage collection module is further configured to select the block based partially on a size of valid data from the block and the block is selected for the garbage collection operation in response to one or more of:

the block having a highest hit count out of blocks having a lowest amount of valid data;

the block having a lowest amount of valid data out of a group of blocks selected as having both less than a threshold amount of valid data and more than a threshold hit count;

the block having a highest hit count out of a group of blocks selected as having both less than a threshold amount of valid data and more than a threshold hit count; and

the block having a highest hit count out of a largest group of blocks having an amount of valid data within a predetermined valid data range of each other.

16. The apparatus of claim 13 , wherein the mapping module, the hit count module, and the garbage collection module comprise one or more of logic hardware and executable program code stored by a non-transitory computer readable storage medium.

17. An apparatus comprising:

means for paging logical-to-physical mappings from a volatile memory to a non-volatile memory;

means for ranking blocks of the non-volatile memory at least partially based on how many of the logical-to-physical mappings for the blocks are estimated to be stored in the volatile memory; and

means for performing a storage capacity recovery operation on a block of the blocks of the non-volatile memory that is selected based at least partially on the ranking of the blocks and in response to the block having a lowest amount of valid data out of a group of blocks selected as having both less than a threshold amount of valid data and more than a threshold number of mappings estimated to be stored in the volatile memory for the storage capacity recovery operation, the estimate determined based on a tracked hit count and a tracked valid data count for the selected region.

18. The apparatus of claim 17 , further comprising means for tracking, per block of the non-volatile memory, how many of the logical-to-physical mappings for the blocks are estimated to be stored in the volatile memory.

19. The apparatus of claim 17 , further comprising means for determining which data of the block is valid based on the logical-to-physical mappings such that performing the storage capacity recovery operation for the block is faster than performing a storage capacity recovery operation on another block with a lower number of mappings estimated to be stored in the volatile memory than the block.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2020
From: XIE, HONGMEI; GORRLE, DHANUNJAYA RAO; KARKI, AAJNA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053577/0829 →
Cited By (2)
US 12,639,201 US 12,693,969