IP Library Granted Patent US 11,537,326
Granted Patent B2
US 11,537,326 · App. 17/182,032 · Granted Dec 27, 2022

Relocation flow using CbA technology

Inventors: Uri Peltz (Hod Hasharon, IL); Karin Inbar (Ramat Hasharon, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0604G06F3/0679G06F11/1068G06F12/10G11C16/26
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Quick Facts
Patent No.
US 11,537,326
App. No.
17/182,032
Granted
Dec 27, 2022
Kind
B2
Abstract

The present disclosure generally relates to efficiently relocating data within a data storage device. By implementing an error correction code (ECC) module in a complementary metal oxide semiconductor (CMOS) chip for each memory die within a memory array of a memory device, the data can be relocated more efficiently. The ECC decodes the codewords at the memory die. The metadata is then extracted from the decoded codewords and transferred to a controller of the data storage device. A flash translation layer (FTL) module at the controller then checks whether the data is valid by comparing the received metadata to FTL tables. If the metadata indicates the data is valid, then the data is relocated.

Claims (39)

1. A data storage device, comprising:

a controller; and

a non-volatile memory device coupled to the controller, wherein the non-volatile memory device is configured to:

decode data;

extract metadata from the decoded data; and

transfer the extracted metadata to the controller, and wherein the non-volatile memory device comprises:

at least one memory die; and

at least one complementary metal oxide semiconductor (CMOS) device coupled to the at least one memory die, wherein the CMOS device comprises an error correction code (ECC) unit.

2. The data storage device of claim 1 , wherein a number of CMOS devices is equal to a number of memory dies.

3. The data storage device of claim 1 , wherein the at least one memory die comprises a plurality of memory dies, wherein the at least one CMOS device comprises a plurality of CMOS devices, and wherein the plurality of memory dies and the plurality of CMOS devices are vertically arranged in an alternating fashion.

4. The data storage device of claim 1 , wherein the at least one CMOS device comprises at least one sense amplifier and at least one latch.

5. The data storage device of claim 1 , wherein the controller includes a flash translation layer (FTL) module.

6. A data storage device, comprising:

a controller; and

a non-volatile memory device coupled to the controller, wherein the non-volatile memory device comprises:

at least one memory die; and

at least one complementary metal oxide semiconductor (CMOS) device coupled to the at least one memory die, wherein the CMOS device comprises an error correction code (ECC) unit, wherein the ECC unit comprises a flash translation layer (FTL) module, an encoder, and a decoder.

7. A data storage device, comprising:

a controller; and

a non-volatile memory device coupled to the controller, wherein the non-volatile memory device is configured to:

decode data;

extract metadata from the decoded data; and

transfer the extracted metadata to the controller.

8. The data storage device of claim 7 , wherein the controller is configured to compare the extracted metadata to data stored in a flash translation layer (FTL) table.

9. The data storage device of claim 8 , wherein the non-volatile memory device is further configured to transfer valid data to the controller in response to the comparing.

10. The data storage device of claim 9 , wherein the controller is configured to relocate the valid data to a different non-volatile memory device.

11. The data storage device of claim 9 , wherein the non-volatile memory device is further configured to assign a new logical block address (LBA) to valid data.

12. The data storage device of claim 11 , wherein the non-volatile memory device is further configured to encode a new codeword with new metadata header for the new LBA.

13. The data storage device of claim 12 , wherein the non-volatile memory device is further configured to program the new codeword to a new physical block address (PBA).

14. The data storage device of claim 13 , wherein the controller is further configured to update a flash translation layer (FTL) table with the new LBA and the new PBA.

15. A data storage device, comprising:

a controller; and

a non-volatile memory device coupled to the controller, wherein the non-volatile memory device comprises:

means for decoding data stored in the non-volatile memory device;

means for extracting metadata from decoded data; and

means for sending the extracted metadata to the controller.

16. The data storage device of claim 15 , wherein the non-volatile memory device comprises a first flash translation layer (FTL) module.

17. The data storage device of claim 16 , wherein the controller comprises a second FTL module distinct from the first FTL module.

18. The data storage device of claim 15 , wherein the controller is configured to compare extracted metadata to data stored in a flash translation layer (FTL) table in the controller.

Assignments (11)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2021
From: PELTZ, URI; INBAR, KARIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055417/0110 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2021
From: PELTZ, URI; INBAR, KARIN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055365/0314 →