Granted Patent B2

US 10,884,664 · App. 16/354,053 · Granted Jan 5, 2021

Abstract

Claims (50)

1. A memory system comprising:

a memory comprising a first executable memory cell; and

a compilation unit configured to:

receive a sequence of instructions from a host device;

convert the sequence of instructions into an execution stream comprising a continuous stream of code and data;

load a first code from the execution stream into a code portion of the first executable memory cell; and

load a first data from the execution stream into a data portion of the first executable memory cell;

wherein the first executable memory cell is configured to apply the first code to the first data via an arithmetic and logic unit of the first executable memory cell.

2. The memory system of claim 1 , wherein the execution stream comprises a plurality of cells, each comprising either code or data.

3. The memory system of claim 1 , wherein the execution stream comprises a data stream and a code stream.

4. The memory system of claim 1 , wherein the compilation unit is configured to determine that a first instruction in the sequence of instructions comprises a plurality of sub-codes, and wherein the compilation unit is further configured to store each of the plurality of sub-codes in the execution stream in a designated sequence.

5. The memory system of claim 4 , wherein each of the plurality of sub-codes is executed by the first executable memory cell in the designated sequence.

6. The memory system of claim 1 , wherein:

the memory further comprises a second executable memory cell; and

the compilation unit is further configured to:

receive indication that the application of the first code to the first data in the first executable memory cell is complete;

load a second code in a code portion of the second executable memory cell upon receiving the indication of completion; and

load a second data in a data portion of the second executable memory cell upon receiving the indication of completion.

7. The memory system of claim 1 , wherein the execution stream comprises a plurality of sub-codes and a plurality of data, wherein each of the plurality of sub-codes is associated with one of the plurality of data to form a plurality of code/data pairs, and wherein each of the plurality of code/data pairs is associated with one executable memory cell for execution.

8. The memory system of claim 7 , wherein each of the plurality of code/data pairs is executed sequentially in a designated sequence.

9. The memory system of claim 7 , wherein each of the plurality of code/data pairs is executed in parallel.

10. The memory system of claim 1 , wherein a two operand operation is performed using a shifting operation in the execution stream.

11. A memory system comprising:

a memory comprising a first executable memory cell; and

a compilation unit configured to:

create a code stream from a sequence of instructions, wherein the code stream comprises a plurality of code cells, each of the plurality of code cells storing a sub-code;

create a data stream from the sequence of instructions for storing a first operand and a second operand;

load a first sub-code into the first executable memory cell, wherein the first sub-code is stored in a first code cell of the plurality of code cells;

load the first operand into the first executable memory cell; and

shift the first sub-code from the first code cell to a second code cell of the plurality of code cells.

12. The memory system of claim 11 , wherein the compilation unit is further configured to:

load a second sub-code in the first code cell;

load the second sub-code into the first executable memory cell;

load the first sub-code from the second code cell to a second executable memory cell of the memory; and

shift the second sub-code to the second code cell.

13. The memory system of claim 11 , wherein the compilation unit is further configured to load the second operand into a second executable memory cell of the memory.

14. The memory system of claim 13 , wherein the first executable memory cell and the second executable memory cell together perform a two operand operation.

15. A non-transitory computer-readable media including computer-executable instructions embodied thereon that, when executed by a processor, cause the processor to perform a process comprising:

receiving a sequence of instructions;

converting the sequence of instructions to create an execution stream comprising a continuous stream of code and data;

loading a first code from the execution stream into a code portion of a first executable memory cell;

loading a first data from the execution stream into a data portion of the first executable memory cell; and

applying the first code to the first data via an arithmetic and logic unit of the first executable memory cell.

16. The non-transitory computer-readable media of claim 15 , wherein the process further comprises creating a single execution stream comprising code interleaved with data.

17. The non-transitory computer-readable media of claim 15 , wherein the process further comprises creating a code stream and a data stream.

18. The non-transitory computer-readable media of claim 15 , wherein a first instruction in the sequence of instructions comprises a plurality of sub-codes to be executed in a designated sequence, and wherein the execution stream stores the plurality of sub-codes in the designated sequence.

19. The non-transitory computer-readable media of claim 15 , wherein the execution stream comprises a plurality of cells, and wherein each of the plurality of cells is associated with one executable memory cell.

20. The non-transitory computer-readable media of claim 15 , wherein the process further comprises:

loading a second code in a code portion of a second executable memory cell upon receiving an indication of completion of a first operation being performed by the first executable memory cell; and

loading a second data in a data portion of the second executable memory cell upon receiving the indication of completion of the first operation.

Assignments (10)