Memory device containing selector with current focusing layer and methods of making the same
A memory cell includes an ovonic threshold switch (OTS) selector containing a first electrode, a second electrode, an OTS located between the first electrode and the second electrode, and a current focusing layer containing discrete electrically conductive current focusing regions having a width of 30 nm or less located between the first electrode and the OTS, and a memory device located in electrical series with the OTS selector.
1. A memory cell, comprising:
an ovonic threshold switch (OTS) selector comprising:
a first electrode;
a second electrode;
an OTS located between the first electrode and the second electrode; and
a current focusing layer comprising discrete electrically conductive current focusing regions having a width of 30 nm or less located between the first electrode and the OTS; and
a memory device located in electrical series with the OTS selector.
2. The memory cell of claim 1 , wherein the discrete electrically conductive current focusing regions have a width of 0.5 nm to 20 nm.
3. The memory cell of claim 1 , wherein the current focusing layer comprises an electrically conductive dusting layer, and the discrete electrically conductive current focusing regions comprise electrically conductive nanoclusters of the dusting layer.
4. The memory cell of claim 3 , wherein the electrically conductive nanoclusters comprise an elemental metal selected from Ti, Zr, Ir, Mg, Pt, W, Ta, Hf, Cr, Fe, Cu, Nb, Mo, Sc, Y, Pd, Au, Os, Ru, or Rh, or an electrically conductive metal nitride.
5. The memory cell of claim 4 , wherein the electrically conductive nanoclusters are located on a metal layer of the first electrode which is immiscible with a material of the conductive nanoclusters.
6. The memory cell of claim 5 , wherein the electrically conductive nanoclusters and the metal layer comprise an immiscible metal layer pair selected from Zr/Ti, Au/Cr, Cu/Nb, Fe/Os, Fe/Ru, Mo/Sc, Os/Pt, Sc/Y, or Ti/Zr.
7. The memory cell of claim 3 , wherein the OTS surrounds and directly contacts the electrically conductive nanoclusters.
8. The memory cell of claim 3 , wherein:
the electrically conductive nanoclusters are embedded in an electrically insulating layer such that surface of the electrically conductive nanoclusters are exposed in a surface of the insulating layer which directly contacts the OTS; and
the OTS directly contacts the exposed surface of the electrically conductive nanoclusters.
9. The memory cell of claim 1 , wherein the current focusing layer comprises a metal-dielectric composite layer, and the discrete electrically conductive current focusing regions comprise metal phase regions embedded in a dielectric matrix of the metal-dielectric composite layer.
10. The memory cell of claim 9 , wherein:
the metal phase regions comprise copper, silver, gold, indium, or alloys thereof; and
the dielectric matrix comprises alumina, zirconia, stabilized zirconia or silicon oxide.
11. The memory cell of claim 1 , wherein the current focusing layer comprises a filamentary breakdown layer which forms electrically conductive filaments upon application of a current and/or voltage across the filamentary breakdown layer, and the discrete electrically conductive current focusing regions comprise the electrically conductive filaments.
12. The memory cell of claim 11 , further comprising:
a source electrode located between the first electrode and the filamentary breakdown layer; and
a buffer electrode located between the filamentary breakdown layer and the OTS.
13. The memory cell of claim 12 , wherein:
the filamentary breakdown layer comprises a stoichiometric or non-stoichiometric dielectric or semiconductor material selected from SiO x , TaO x , TiO x , GeO x , SnO x , HfO x , MgO x , SiN x , AlO x , VO x , NiO x , GeSe, GeTe, ZrO x , ZrTe or ternary or quaternary compounds thereof;
the source electrode comprises a metal layer selected from Ta, Cu, Ti, Au or Ag; and
the buffer electrode comprises Ru, Rh or a carbon based material.
14. The memory cell of claim 1 , wherein the memory device comprises a magnetic tunnel junction or a phase change memory device.
15. A method of operating the memory cell of claim 1 , comprising applying a voltage or current across the OTS between the first electrode and the second electrode to form an electrically conductive filament through the OTS between the first electrode and the second electrode to switch the OTS selector from a higher resistance state into a lower resistance state, wherein the discrete electrically conductive current focusing regions focus current injection into the OTS at one or more points which confines the current in the OTS and forms the electrically conductive filaments in specific regions of the OTS adjacent to the electrically conductive current focusing regions.
16. A method of making a memory cell, comprising:
forming ovonic threshold switch (OTS) selector comprising:
a first electrode;
a second electrode;
an OTS located between the first electrode and the second electrode; and
a current focusing layer comprising discrete electrically conductive current focusing regions having a width of 30 nm or less located between the first electrode and the OTS; and
forming a memory device located in electrical series with the OTS selector.
17. The method of claim 16 , wherein the current focusing layer comprises an electrically conductive dusting layer, and the discrete electrically conductive current focusing regions comprise electrically conductive nanoclusters of the dusting layer.
18. The method of claim 17 , further comprising:
depositing a continuous layer of a first metal on the first electrode; and
depositing a second metal which is immiscible with the first metal on the continuous layer to form the electrically conductive nanoclusters of the second metal on the continuous layer.
19. The method of claim 17 , further comprising depositing a metal on a carbon based material, wherein the carbon based material changes a local morphology of the metal to form the electrically conductive nanoclusters.
20. The method of claim 17 , further comprising sputter etching the electrically conductive dusting layer to form the electrically conductive nanoclusters.