Bifurcated memory die module semiconductor device
View Patent ↗A semiconductor device is disclosed including one or more integrated memory modules. Each integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the first die may be flip-chip bonded to the second die.
1. An integrated memory module comprising:
a first semiconductor die;
a second semiconductor die flip-chip bonded to a surface of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die;
wherein the first and second coupled semiconductor dies together are configured as an integrated memory.
2. The integrated memory module of claim 1 , wherein the first semiconductor die comprises a plurality of memory cells.
3. The integrated memory module of claim 2 , wherein the second semiconductor die comprises a control circuit for controlling access of the plurality of memory cells.
4. The integrated memory module of claim 3 , wherein the control circuit comprises a complementary metal—oxide—semiconductor integrated circuit.
5. The integrated memory module of claim 1 , wherein the first and second dies together are configured as a nonvolatile memory device.
6. The integrated memory module of claim 5 , wherein the nonvolatile memory device comprises one of a NAND flash memory device, a Magnetic random access memory (RAM) device, a Phase Change RAM device and a resistive RAM device.
7. The integrated memory module of claim 1 , wherein the first semiconductor die comprises a plurality of bonding pads configured to wire bond the first semiconductor die.
8. The integrated memory module of claim 1 , wherein the integrated memory module has a footprint equal to a footprint of the first semiconductor die.
9. The integrated memory module of claim 8 , wherein the second semiconductor die is smaller than the first semiconductor die.
10. The integrated memory module of claim 1 , wherein the second semiconductor die includes a first group of bond pads, on a first surface of the second semiconductor die adjacent the first semiconductor die, for flip-chip bonding of the second semiconductor die to the first semiconductor die.
11. The integrated memory module of claim 10 , further comprising a second set of bond pads on a second surface of the first semiconductor die opposite the first surface.
12. A semiconductor device, comprising:
a substrate;
a first integrated memory module affixed to the substrate, comprising:
a first semiconductor die including a surface having a plurality of die bond pads;
a second semiconductor die bonded to the surface of the first semiconductor die adjacent the plurality of die bond pads;
wherein the first and second coupled semiconductor dies together are configured as an integrated memory.
13. The semiconductor device of claim 12 , further comprising a third semiconductor die, mounted on the surface of the first semiconductor die, adjacent the second semiconductor die.
14. The semiconductor device of claim 13 , wherein the third semiconductor die comprises a memory die.
15. The semiconductor device of claim 13 , wherein the third semiconductor die comprises a plurality of memory cells, the semiconductor device further comprising a fourth semiconductor die bonded to the surface of the third semiconductor, wherein the third and fourth coupled semiconductor dies together are configured as an integrated memory.
16. The semiconductor device of claim 15 , wherein the fourth semiconductor die is flip-chip bonded to the third semiconductor die.
17. The semiconductor device of claim 15 , wherein the fourth semiconductor die is electrically connected to the third semiconductor die using through silicon vias.
18. The semiconductor device of claim 12 , further comprising a wire bond extending between a contact pad on the substrate and a die bond pad on the first semiconductor die.
19. The semiconductor device of claim 12 , further comprising a wire bond extending between a contact pad on the substrate and a die bond pad on the second semiconductor die.
20. A semiconductor device, comprising:
a substrate;
a first integrated memory module affixed to the substrate, comprising:
a first semiconductor die including a surface having a first plurality of die bond pads;
a second semiconductor die bonded to the surface of the first semiconductor die adjacent the plurality of die bond pads;
wherein the first and second coupled semiconductor dies together are configured as an integrated memory;
a third semiconductor die, mounted to the first integrated memory module, adjacent the second semiconductor die, the third semiconductor die comprising a second plurality of die bond pads; and
wire bonds connected between the first and second pluralities of die bond pads, the wire bonds extending over the second semiconductor die.
21. The semiconductor device of claim 20 , wherein the third semiconductor die is mounted on the first surface of the first semiconductor die.
22. The semiconductor device of claim 20 , wherein the third semiconductor die is mounted on a surface of the second semiconductor die.
23. The semiconductor device of claim 20 , wherein the third semiconductor die comprises a memory die.
24. The semiconductor device of claim 20 , wherein the third semiconductor die comprises a plurality of memory cells, the semiconductor device further comprising a fourth semiconductor die bonded to the surface of the third semiconductor, wherein the third and fourth coupled semiconductor dies together are configured as an integrated memory.
25. The semiconductor device of claim 24 , wherein the fourth semiconductor die is flip-chip bonded to the third semiconductor die.
26. An integrated memory module comprising:
a first semiconductor die comprising memory means;
a second semiconductor die comprising logic circuit means, the second semiconductor die flip-chip bonded to a surface of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die;
wherein the first and second coupled semiconductor dies together are configured as an integrated memory.