Measurement, calibration and tuning of memory bus duty cycle
A method and apparatus for dynamically monitoring, measuring, and adjusting a clock duty cycle of an operating storage device is disclosed. A storage device includes a measuring circuit comprising a plurality of flip flop registers coupled to a first input line, with each flip flop register having a first input and a second input. One or more delay taps are coupled to each flip flop register, and are disposed on a second input line. While the device operates, a clock signal is input directly into the first input of each flip flop register via the first input line. Simultaneously, the clock signal is input into the second input of each flip flop register through the one or more delay taps via the second input line. The flip flop registers are then read to determine the clock duty cycle of the device, and the clock frequency is adjusted as needed.
1. A storage device, comprising:
one or more memory devices;
a controller coupled to the one or more memory devices; and
a measuring circuit coupled to the controller, the measuring circuit comprising:
a plurality of consecutive delay taps;
a plurality of flip flop registers, wherein each flip flop register of the plurality of flip flop registers comprises a first input and a second input;
a first input line coupled directly to the first input of each flip flop register of the plurality of flip flop registers;
a second input line coupled to the second input of each flip flop register of the plurality of flip flop registers through consecutive delay taps of the plurality of consecutive delay taps, wherein each consecutive delay tap has a constant delay;
a variable delay circuit coupled to the second input line, wherein the variable delay circuit is disposed before a first delay tap of the plurality of consecutive delay taps; and
a measurement signal configured to enable a measurement of a clock duty cycle of the measuring circuit.
2. The storage device of claim 1 , wherein the measuring circuit is configured to measure a clock duty cycle of the storage device.
3. The storage device of claim 2 , wherein the measuring circuit is configured to adjust a clock frequency of the storage device.
4. The storage device of claim 1 , wherein the variable delay circuit comprises a plurality of delay taps.
5. The storage device of claim 4 , wherein the variable delay circuit is configured to increase a delay to a signal input into the second input line.
6. The storage device of claim 1 , wherein the second input line is coupled to the consecutive delay taps through the variable delay circuit.
7. The storage device of claim 1 , wherein the same clock signal is input into both the first input line and the second input line.
8. A method of operating a storage device, comprising:
inputting a first signal into a plurality of flip flop registers of a measuring circuit, the first signal being directly input into a first input of each of the flip flop registers of the plurality of flip flop registers;
inputting, simultaneously, a second signal into a plurality of delay taps, wherein one or more delay taps are coupled to each of the flip flop registers of the plurality of flip flop registers, and wherein the second signal passes through each of the one or more delay taps to a second input of each flip flop register of the plurality of flip flop registers, wherein a variable delay circuit is coupled to the second input line, wherein the variable delay circuit is disposed before a first delay tap of the one or more delay taps;
reading the plurality of flip flop registers to measure a clock duty cycle; and
calibrating the clock duty cycle in response to the measurement while operating the storage device.
9. The method of claim 8 , further comprising resetting the plurality of flip flop registers before inputting the first signal.
10. The method of claim 8 , wherein the plurality of flip flop registers is measured using a measurement signal.
11. The method of claim 8 , wherein the first signal and the second signal are a clock signal.
12. The method of claim 8 , further comprising switching the storage device to an active state before inputting the first signal.
13. The method of claim 8 , wherein calibrating the clock duty cycle comprises adjusting a clock frequency of the storage device.