IP Library Granted Patent US 10,636,495
Granted Patent B2
US 10,636,495 · App. 16/052,523 · Granted Apr 28, 2020

Adjustable read retry order based on decoding success trend

Inventors: Niang-Chu Chen (Irvine, CA); Jun Tao (Ladera Ranch, CA)
Assignee: Western Digital Technologies, Inc.
G11C16/26G11C8/10G11C11/4087G11C11/5642G11C16/08G11C29/42G11C29/44G11C29/52H03M13/1102G11C16/0483G11C2211/5632
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Quick Facts
Patent No.
US 10,636,495
App. No.
16/052,523
Granted
Apr 28, 2020
Kind
B2
Abstract

Methods, systems, and media for decoding data are described. A sequence of read-level voltages for decoding operations may be determined based on a trend of decoding success indicators, including a first decoding success indicator and a second decoding success indicator. The first decoding success indicator is obtained from a more recent successful decoding operation. The first one of the sequence may be set to a read-level voltage of the first decoding success indicator. If the read-level voltage of the first decoding success indicator is less than a read-level voltage of the second decoding success indicator, then the trend is decreasing, and the second one of the sequence may be set to a read-level voltage less than that of the first one of the sequence. After executing one or more decoding operations, the decoding success indicators may be updated based on the read-level voltage of the current successful decoding operation.

Claims (44)

1. A data storage system, comprising:

a non-volatile memory device; and

a controller configured to cause:

setting a sequence of read-level voltages based on a trend of a set of decoding success indicators that comprise at least a first decoding success indicator and a second decoding success indicator obtained from at least two recent successful decoding operations;

executing one or more decoding operations to decode data read from a plurality of memory cells based on the sequence of read-level voltages;

returning decoded data from one of the one or more decoding operations when the one of the one or more decoding operations is successful; and

maintaining the set of decoding success indicators, based at least on a successful one of the one or more decoding operations,

wherein setting the sequence of read-level voltages comprises setting a first read-level voltage, which is a first one in the sequence, to a read-level voltage corresponding to a more recent one of the first and second decoding success indicators.

2. The data storage system of claim 1 , wherein the trend of the set of decoding success indicators is decreasing when a read-level voltage corresponding to the first decoding success indicator is less than a read-level voltage corresponding to the second decoding success indicator, and wherein the first decoding success indicator is more recent than the second decoding success indicator.

3. The data storage system of claim 2 , wherein setting the sequence of read-level voltages comprises setting a second read-level voltage of the sequence to a read-level voltage that is less than the first read-level voltage when the trend of the set of decoding success indicators is decreasing, and

wherein a first one of the one or more decoding operations is based on the first read-level voltage, and a subsequent one of the one or more decoding operations is based on the second read-level voltage.

4. The data storage system of claim 2 , wherein the read-level voltages comprise a lowest read-level voltage among the read-level voltages, and wherein when one read-level voltage in the sequence is the lowest read-level voltage, a next read-level voltage in the sequence is a read-level voltage next to and higher than the first read-level voltage.

5. The data storage system of claim 1 , wherein the read-level voltages comprise a lowest read-level voltage and a highest read-level voltage among the read-level voltages, and wherein when one read-level voltage in the sequence is the lowest or the highest read-level voltage, the controller is configured to determine a next read-level voltage in the sequence based on a direction reverse of the trend.

6. The data storage system of claim 1 , wherein maintaining the set of decoding success indicators comprises:

when a read-level voltage used for the successful one of the one or more decoding operations is different from a read-level voltage corresponding to the first decoding success indicator,

setting a read-level voltage corresponding to the second decoding success indicator to the read-level voltage corresponding to the first decoding success indicator; and

setting the read-level voltage corresponding to the first decoding success indicator to the read-level voltage used for the successful one of the one or more decoding operations.

7. A non-transitory machine-readable medium including machine-executable instructions thereon that, when executed by a processor, perform a method comprising:

determining a trend of a set of decoding success indicators based on a voltage trend between a first read-level voltage corresponding to a first decoding success indicator and a second read-level voltage corresponding to a second decoding success indicator, wherein the first and second read-level voltages are different;

setting a sequence of read-level voltages based on the trend of the set of decoding success indicators that comprise at least the first decoding success indicator and the second decoding success indicator;

performing one or more decoding operations to decode data read from a plurality of memory cells based on the sequence of read-level voltages;

returning decoded data from one of the one or more decoding operations when the one of the one or more decoding operations is successful; and

maintaining the set of decoding success indicators, based at least on a successful one of the one or more decoding operations.

8. The non-transitory machine-readable medium of claim 7 , wherein the first decoding success indicator is more recent than the second decoding success indicator, and wherein the trend of the set of decoding success indicators is decreasing when the first read-level voltage corresponding to the first decoding success indicator is less than th second read-level voltage corresponding to the second decoding success indicator.

9. The non-transitory machine-readable medium of claim 7 , wherein the read-level voltages in the sequence comprise a lowest read-level voltage and a highest read-level voltage among the read-level voltages, and wherein when one read-level voltage in the sequence is the lowest or the highest read-level voltage, the method comprises determining a next read-level voltage in the sequence based on a direction reverse of the trend.

10. The non-transitory machine-readable medium of claim 7 , wherein maintaining the set of decoding success indicators comprises:

when a read-level voltage used for the successful one of the one or more decoding operations is different from the first read-level voltage corresponding to the first decoding success indicator,

setting the second read-level voltage corresponding to the second decoding success indicator to the first read-level voltage corresponding to the first decoding success indicator; and

setting the first read-level voltage corresponding to the first decoding success indicator to the read-level voltage used for the successful one of the one or more decoding operations.

11. The non-transitory machine-readable medium of claim 7 , wherein setting the sequence of read-level voltages comprises setting a first one, in the sequence of read-level voltages, to the first read-level voltage corresponding to the first decoding success indicator, and wherein the first decoding success indicator is a more recent one of the first and second decoding success indicators.

12. The non-transitory machine-readable medium of claim 11 , wherein if the first read-level voltage corresponding to the first decoding success indicator is less than the second read-level voltage corresponding to the second decoding success indicator, then setting the sequence of read-level voltages comprises setting a second one, in the sequence of read-level voltages, to a read-level voltage less than the first read-level voltage and less than the second read-level voltage.

13. A data storage system, comprising:

means for setting a sequence of read-level voltages using a trend of a set of decoding success indicators that comprise at least a first decoding success indicator and a second decoding success indicator obtained from at least two recent successful decoding operations;

means for executing one or more decoding operations to decode data read from a plurality of memory cells based on the sequence of read-level voltages;

means for providing decoded data from one of the one or more decoding operations when the one of the one or more decoding operations is successful; and

means for maintaining the set of decoding success indicators, based at least on a successful one of the one or more decoding operations,

wherein the means for setting the sequence of read-level voltages comprises means for determining the trend of the set of decoding success indicators based on a change between a first recent read-level voltage corresponding to the first decoding success indicator and a second recent read-level voltage corresponding to the second decoding success indicator, and wherein the first decoding success indicator is an indicator that is more recent than the second decoding success indicator.

14. The data storage system of claim 13 , wherein when the first recent read-level voltage is less than the second recent read-level voltage, the trend is decreasing, and a voltage level of a second one of the sequence is less than a voltage level of a first one of the sequence.

15. The data storage system of claim 14 , wherein the means for setting the sequence of read-level voltages comprises means for setting the voltage level of the first one of the sequence to the first recent read-level voltage, and when the trend is decreasing, the means for setting the sequence of read-level voltages comprises means for setting the voltage level of the second one of the sequence to a read-level voltage less than the first recent read-level voltage and less than the second recent read-level voltage.

16. The data storage system of claim 13 , wherein the read-level voltages in the sequence comprise a lowest read-level voltage and a highest read-level voltage among the read-level voltages, and wherein when one read-level voltage in the sequence is the lowest or the highest read-level voltage, the means for setting the sequence comprises determining a next read-level voltage in the sequence based on a direction reverse of the trend.

17. The data storage system of claim 13 , wherein means for maintaining the set of decoding success indicators comprises:

when a read-level voltage used for the successful one of the one or more decoding operations is different from a read-level voltage corresponding to the first decoding success indicator,

means for setting a read-level voltage corresponding to the second decoding success indicator to the read-level voltage corresponding to the first decoding success indicator; and

means for setting the read-level voltage corresponding to the first decoding success indicator to the read-level voltage used for the successful one of the one or more decoding operations.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 7, 2018
From: CHEN, NIANG-CHU; TAO, JUN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046573/0963 →
Continuity (2)
Provisional Application 62684157 · Jun 12, 2018
Related Publication 20190378576A1 · Dec 12, 2019
Cited By (2)
US 12,469,573 US 12,500,609