Optimized decoding scheduling in a joint LDPC and RAID decoding scheme
A data storage device includes an error correction code (ECC) ordering system that determines a decoding schedule in which two or more flash memory units (FMUs) that have failed an initial decoding process are to be decoded using a joint decoding scheme. The ECC ordering system generates the decoding schedule based on a metric associated with each FMU. The metric on which the decoding schedule is based is a syndrome weight associated with each FMU or is a combined bit error rate (BER) associated with each FMU. When the decoding schedule has been generated, the ECC ordering system causes a joint decoding operation to be executed on the FMUs in the order specified by the decoding schedule.
1 . A method, comprising:
identifying two or more flash memory units (FMUs) associated with a data storage device that have failed an initial decoding operation executed by an error code correction system of the data storage device;
determining a metric associated with each of the two or more FMUs;
generating a decoding schedule for the two or more FMUs based, at least in part, on the metric associated with each of the two or more FMUs, the decoding schedule indicating an order in which the two or more FMUs will be decoded using a joint decoding scheme, the joint decoding scheme comprising a first decoding scheme and a second decoding scheme;
executing a joint decoding operation on a first FMU of the two or more FMUs in the order specified by the generated decoding schedule and using the joint decoding scheme; and
determining whether the joint decoding operation on the first FMU of the two or more FMUs is successful.
2 . The method of claim 1 , wherein the first decoding scheme is a low-density parity check (LDPC) decoding scheme.
3 . The method of claim 1 , wherein the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme.
4 . The method of claim 1 , further comprising executing the joint decoding operation on a second FMU of the two or more FMUs based, at least in part, on determining the joint decoding operation on the first FMU of the two or more FMUs was successful.
5 . The method of claim 1 , further comprising ending the joint decoding operation based, at least in part, on determining the joint decoding operation on the first FMU of the two or more FMUs was unsuccessful.
6 . The method of claim 1 , wherein the metric is a syndrome weight associated with each FMU of the two or more FMUs.
7 . The method of claim 1 , wherein the metric is a combined bit error rate (BER) associated with each FMU of the two or more FMUs.
8 . The method of claim 1 , wherein each FMU of the two or more FMUs is associated with a stripe.
9 . A data storage device, comprising:
a controller; and
an error correction code (ECC) system associated with the controller and operable to:
execute an initial decoding operation on flash memory units (FMUs) associated with a stripe;
determine whether any FMUs failed the initial decoding operation; and
based, at least in part, on determining two or more FMUs failed the initial decoding operation:
determine a metric associated with each of the two or more FMUs;
determine, based at least in part, on the metric associated with each of the two or more FMUs, an order in which each of the two or more FMUs will undergo a joint decoding operation using a joint decoding scheme, the joint decoding scheme comprising a first decoding scheme and a second decoding scheme;
execute the joint decoding operation on the two or more FMUs in the determined order; and
determine whether the joint decoding operation on a first FMU of the two or more FMUs is successful.
10 . The data storage device of claim 9 , wherein the ECC system is further operable to execute the joint decoding operation on a second FMU of the two or more FMUs based, at least in part, on a determination that the joint decoding operation on the first FMU of the two or more FMUs is successful.
11 . The data storage device of claim 9 , wherein the ECC system is further operable to end the joint decoding operation based, at least in part, on a determination that the joint decoding operation on the first FMU of the two or more FMUs was unsuccessful.
12 . The data storage device of claim 9 , wherein the first decoding scheme is a low-density parity check (LDPC) decoding scheme.
13 . The data storage device of claim 9 , wherein the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme.
14 . The data storage device of claim 9 , wherein the metric is a syndrome weight associated with each FMU of the two or more FMUs.
15 . The data storage device of claim 9 , wherein the metric is a combined bit error rate (BER) associated with each FMU of the two or more FMUs.
16 . A data storage device, comprising:
a control means; and
an error correction means associated with the control means and operable to:
determine whether two or more memory means associated with the data storage device failed an initial decoding operation;
based, at least in part, on a determination that two or more memory means failed the initial decoding operation:
determine a first metric associated with a first memory means of the two or more memory means;
determine a second metric associated with a second memory means of the two or more memory means;
compare the first metric and the second metric;
generate a decoding schedule based, at least in part, on comparing the first metric and the second metric;
execute a joint decoding operation using a joint decoding scheme on at least one of the first memory means and the second memory means using the decoding schedule, the joint decoding scheme comprising a first decoding scheme and a second decoding scheme; and
determine whether the joint decoding operation on the at least one of the first memory means and the second memory means is successful.
17 . The data storage device of claim 16 , wherein the error correction means is further operable to execute the joint decoding operation on another memory means based, at least in part, on a determination that the joint decoding operation on the at least one of the first memory means and the second memory means was successful.
18 . The data storage device of claim 16 , wherein the error correction means is further operable to end the joint decoding operation based, at least in part, on a determination that the joint decoding operation on the at least one of the first memory means and the second memory means was unsuccessful.
19 . The data storage device of claim 16 , wherein the first decoding scheme is a low-density parity check (LDPC) decoding scheme and the second decoding scheme is a redundant array of independent dies (RAID) decoding scheme.
20 . The data storage device of claim 16 , wherein the metric is a combined bit error rate (BER) associated with each of the two or more failed memory means.