IP Library Granted Patent US 11,854,603
Granted Patent B2
US 11,854,603 · App. 17/540,682 · Granted Dec 26, 2023

Logical to encoded value table in data storage device

Inventors: Atif Hussain (Longmont, CO); Vivek Shivhare (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
G11C11/4087G06F12/0246G11C11/4085H03K19/17728G06F2212/7201
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Quick Facts
Patent No.
US 11,854,603
App. No.
17/540,682
Granted
Dec 26, 2023
Kind
B2
Abstract

A data storage device including, in one implementation, a memory device and a controller configured to configured to retrieve a plurality of physical memory addresses from a first lookup table in the non-volatile memory. Each physical memory address is a combination of a word line and a string number of the non-volatile memory and the each physical memory address has a first number of bits. The controller is further configured to generate a plurality of encoded values by encoding the plurality of physical memory addresses. Each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits. The controller is further configured to store the plurality of encoded values in the first lookup table, generate a logical to encoded value look-up table with the plurality of encoded values, and store the logical to encoded value look-up table in the memory.

Claims (67)

1. A data storage device, comprising:

a non-volatile memory; and

a controller including a memory and an electronic processor, the controller coupled to the non-volatile memory, and the electronic processor configured to:

retrieve a plurality of physical memory addresses from a first lookup table in the non-volatile memory, wherein each physical memory address is a combination of a word line and a string number of the non-volatile memory, the each physical memory address has a first number of bits,

generate a plurality of encoded values by encoding the plurality of physical memory addresses, each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits,

store the plurality of encoded values in the first lookup table,

generate a logical to encoded value look-up table with the plurality of encoded values, and

store the logical to encoded value look-up table in the memory.

2. The data storage device of claim 1 , wherein the controller is further configured to:

receive a plurality of logical addresses, and

update the logical to encoded value look-up table with the plurality of logical addresses.

3. The data storage device of claim 2 , wherein the controller is further configured to:

receive a request to write data to one or more of the plurality of logical addresses,

determine one or more encoded values corresponding to the one or more of the plurality of logical addresses,

decode the one or more encoded values to determine one or more physical memory addresses, and

control the non-volatile memory to write the data to the one or more physical memory addresses.

4. The data storage device of claim 2 , wherein the controller is further configured to:

receive a request to read data at one or more of the plurality of logical addresses,

determine one or more encoded values corresponding to the one or more of the plurality of logical addresses,

decode the one or more encoded values to determine one or more physical memory addresses, and

control the non-volatile memory to output the data from the one or more physical memory addresses.

5. The data storage device of claim 1 , wherein the plurality of physical memory addresses are physical memory addresses that are configured to be used in the non-volatile memory.

6. The data storage device of claim 1 , wherein the first number of bits is 11 bits and the second number of bits is 10 bits.

7. The data storage device of claim 1 , wherein the plurality of encoded values includes values from 0 to 799.

8. A method comprising:

retrieving, with a data storage controller, a plurality of physical memory addresses from a first lookup table in a non-volatile memory, wherein each physical memory address is a combination of a word line and a string number of the non-volatile memory, the each physical memory address has a first number of bits,

generating, with the data storage controller, a plurality of encoded values by encoding the plurality of physical memory addresses, each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits,

storing, with the data storage controller, the plurality of encoded values in the first lookup table,

generating, with the data storage controller, a logical to encoded value look-up table with the plurality of encoded values, and

storing, with the data storage controller, the logical to encoded value look-up table in a memory of the data storage controller.

9. The method of claim 8 further comprising:

receiving, with the data storage controller, a plurality of logical addresses; and

updating, with the data storage controller, the logical to encoded value look-up table with the plurality of logical addresses.

10. The method of claim 9 further comprising:

receiving, with the data storage controller, a request to write data to one or more of the plurality of logical addresses,

determining, with the data storage controller, one or more encoded values corresponding to the one or more of the plurality of logical addresses,

decoding, with the data storage controller, the one or more encoded values to determine one or more physical memory addresses, and

controlling, with the data storage controller, the non-volatile memory to write the data to the one or more physical memory addresses.

11. The method of claim 9 further comprising:

receiving, with the data storage controller, a request to read data at one or more of the plurality of logical addresses,

determining, with the data storage controller, one or more encoded values corresponding to the one or more of the plurality of logical addresses,

decoding, with the data storage controller, the one or more encoded values to determine one or more physical memory addresses, and

controlling, with the data storage controller, the non-volatile memory to output the data from the one or more physical memory addresses.

12. The method of claim 8 , wherein the plurality of physical memory addresses are physical memory addresses that are configured to be used in the non-volatile memory.

13. The method of claim 8 , wherein the first number of bits is 11 bits and the second number of bits is 10 bits.

14. The method of claim 8 , wherein the plurality of encoded values includes values from 0 to 799.

15. A non-transitory computer readable medium including instructions that, when executed by a data storage controller, causes the data storage controller to execute a set of operations, the set of operations comprising:

retrieving a plurality of physical memory addresses from a first lookup table in a non-volatile memory, wherein each physical memory address is a combination of a word line and a string number of the non-volatile memory, the each physical memory address has a first number of bits,

generating a plurality of encoded values by encoding the plurality of physical memory addresses, each of the plurality of encoded values has a second number of bits that is smaller than the first number of bits,

storing the plurality of encoded values in the first lookup table,

generating a logical to encoded value look-up table with the plurality of encoded values, and

controlling a memory of the data storage controller to store the logical to encoded value look-up table.

16. The non-transitory computer readable medium of claim 15 , wherein the set of operations further include

receiving a plurality of logical addresses; and

updating the logical to encoded value look-up table with the plurality of logical addresses.

17. The non-transitory computer readable medium of claim 16 , wherein the set of operations further include

receiving a request to write data to one or more of the plurality of logical addresses,

determining one or more encoded values corresponding to the one or more of the plurality of logical addresses,

decoding the one or more encoded values to determine one or more physical memory addresses, and

controlling the non-volatile memory to write the data to the one or more physical memory addresses.

18. The non-transitory computer readable medium of claim 16 , wherein the set of operations further include

receiving a request to read data at one or more of the plurality of logical addresses,

determining one or more encoded values corresponding to the one or more of the plurality of logical addresses,

decoding the one or more encoded values to determine one or more physical memory addresses, and

controlling the non-volatile memory to output the data from the one or more physical memory addresses.

19. The non-transitory computer readable medium of claim 15 , wherein the plurality of physical memory addresses are physical memory addresses that are configured to be used in the non-volatile memory.

20. The non-transitory computer readable medium of claim 15 , wherein the first number of bits is 11 bits and the second number of bits is 10 bits.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 2, 2021
From: HUSSAIN, ATIF; SHIVHARE, VIVEK
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058270/0589 →