Dual SLC/QLC programming and resource releasing
The present disclosure generally relates to improved foggy-fine programming. Rather than initially writing to SLC and then later performing a foggy write to QLC with the data read from SLC and then a fine write to QLC with data re-read from SLC, the foggy write to QLC can be performed in parallel to the initial writing to SLC using the same buffer. Once the foggy write to QLC has completed, and the writing to SLC has also completed, the data buffer can be released. The data written in SLC is then be read from SLC and passes through a relocation buffer for the first and only time to then be written using fine programming to QLC. Thus, the data only passes through the relocation buffer one time and the relocation buffer can be freed to usage after only one pass of the data therethrough.
1. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, the controller configured to:
determine whether a first buffer release request for a buffer has been received, wherein the first buffer release request corresponds to a first programming of data;
determine whether a second buffer release request for the buffer has been received, wherein the second buffer release request corresponds to a second programming of the same data, and wherein the second buffer release request is issued and received independently of the first buffer release request; and
release the buffer to an available buffer pool of buffers upon determining that the first buffer release request and the second buffer release request for the buffer have both been received.
2. The data storage device of claim 1 , wherein the controller is further configured to hold data in the buffer until the buffer has been released.
3. The data storage device of claim 1 , wherein the controller is further configured to not release the buffer if either the first buffer release request or the second buffer release request has not been received.
4. The data storage device of claim 1 , wherein the controller is configured to increment a value of FirstFail from 0 to 1 if the first programming has failed.
5. The data storage device of claim 4 , wherein the controller is configured to increment a value of SecondFail from 0 to 1 if the second programming has failed.
6. The data storage device of claim 5 , wherein the controller is further configured to not release the buffer if either the FirstFail or the SecondFail is equal to 1.
7. The data storage device of claim 1 , wherein the controller is further configured to release the buffer to the available buffer pool of buffers only if both the first buffer release request and the second buffer release request have been received.
8. A data storage device, comprising:
one or more memory devices;
means to determine that a buffer has received two release requests, wherein a first release request of the received two release requests corresponds with a single level cell (SLC) memory program of data, wherein a second release request of the received two release requests corresponds with a multi level cell (MLC) memory program of the same data, and wherein the first release request is issued and received independently of the second release request; and
means to foggy write to MLC memory in parallel with writing to SLC memory.
9. The data storage device of claim 8 , further comprising means to receive the first release request.
10. The data storage device of claim 9 , further comprising means to receive the second release request.
11. The data storage device of claim 10 , further comprising means to release the buffer, wherein the means to release the buffer is configured to release the buffer based upon feedback from the means to determine.
12. The data storage device of claim 8 , further comprising means to read data from SLC memory and fine write the data read from SLC memory to the MLC memory.
13. The data storage device of claim 8 , further comprising means to release a buffer to an available buffer pool.
14. A data storage device, comprising:
one or more memory devices; and
a controller coupled to the one or more memory devices, the controller configured to:
receive a first release request for a buffer, wherein the first buffer release request corresponds to a first programming of data;
receive a second release request for the buffer, the second buffer release request corresponds to a second programming of the same data, wherein the second buffer release request is issued and received independently of the first buffer release request; and
upon receiving both the first release request and the second release request for the buffer, release the buffer to an available buffer pool.
15. The data storage device of claim 14 , wherein the buffer stores data being first programmed to SLC memory and second programmed to MLC memory, and wherein the data being first programmed occurs in parallel to the same data being second programmed.
16. The data storage device of claim 14 , wherein the first release request indicates that either writing data to SLC memory or foggy writing data to MLC memory has completed.
17. The data storage device of claim 16 , wherein the second release request indicates that either the writing the data to the SLC memory or the foggy writing the data to the MLC memory has completed, and wherein the second release request is different than the first release request.
18. The data storage device of claim 14 , wherein releasing the buffer comprises completing both writing data to SLC memory and foggy writing data to MLC memory.
19. The data storage device of claim 18 , wherein fine writing the data to the MLC memory occurs after the foggy writing data to the MLC memory has completed.
20. The data storage device of claim 19 , wherein the fine writing comprises:
reading the data from the SLC memory;
passing the data through a relocation buffer a single time before the fine writing the data to the MLC memory; and
fine writing the data to the MLC memory.