Scaling large drives using enhanced DRAM ECC
View Patent ↗The present disclosure generally relates to solid state storage device and techniques for conserving storage capacity associated therewith. Several embodiments are presented, including a data storage device, data storage controller, and methods for using the same are provided in the subject disclosure. A data storage device includes: a plurality of memory devices, a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices, a memory including a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices, where the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map, respectively, to at least two physical locations in the plurality of memory devices, where the controller is configured to encode each merged entry with an error-correcting code.
1. A data storage device, comprising:
a plurality of memory devices;
a controller coupled to the plurality of memory devices and configured to program data to and read data from the plurality of memory devices; and
a memory comprising a logical-to-physical address translation map configured to enable the controller to determine a physical location of stored data in the plurality of memory devices,
wherein the logical-to-physical address translation map contains at least one entry that merges at least two addresses that map to at least two physical locations in the plurality of memory devices, wherein each of the at least two addresses map to one of the at least two physical locations, and
wherein the controller is configured to encode the at least one entry with an error-correcting code, wherein the error-correcting code is configured to operate as address data of the at least two physical locations.
2. The data storage device according to claim 1 , wherein the at least one entry merges between two addresses and eight addresses that map to at least two physical locations to at least eight physical locations in the plurality of memory devices.
3. The data storage device according to claim 1 , wherein the memory is a volatile memory.
4. The data storage device according to claim 1 , wherein the memory is non-volatile memory.
5. The data storage device according to claim 3 , wherein the memory is DRAM.
6. The data storage device according to claim 4 , wherein the memory is ReRAM.
7. The data storage device according to claim 5 , wherein the controller is configured to transmit additional data at a rate based on a data size of a single address of the at least two physical locations.
8. The data storage device according to claim 7 , wherein the at least one entry includes at least 33 bits in address data.
9. A data storage device controller, comprising:
a processor coupled to a memory and to a plurality of memory devices, each of the plurality of memory devices being configured to store data at a predetermined physical location within the plurality of devices,
wherein the processor is further configured to program data to and read data from the plurality of memory devices, the memory containing a logical-to-physical address translation map configured to enable the processor to determine a physical location of data stored in the predetermined physical location, and
wherein the processor simultaneously encodes at least two entries of the logical-to-physical address translation map with a single error-correcting word, wherein the error-correcting word is configured to operate as address data of the at least two entries.
10. The data storage device according to claim 9 , wherein the processor is further configured to decode additional data containing an address of one of the at least two entries of the logical-to-physical address translation map.
11. The data storage device according to claim 10 , wherein the decoding operation detects between one and two bits in error for the data containing the address.
12. The data storage device according to claim 11 , wherein the decoding operation corrects one bit in error of the data containing the address of one of the at least two entries of the logical-to-physical address translation map.
13. A a data storage device, comprising:
a logical to physical address translation map;
a plurality of entries that map a logical address to a physical location of stored data in a plurality of memory devices,
wherein at least one entry of the plurality of entries merges at least two addresses that map to at least two physical locations in the plurality of memory devices,
wherein the at least one entry is configured to receive an encoding operation by a controller coupled to the plurality of memory devices, and
wherein the encoding operation encodes the at least one entry with an error-correcting code, wherein the error-correcting code is configured to operate as address data of the at least two physical locations.
14. The data storage device according to claim 13 , further comprising:
a plurality of logical indexes pointing to each of a plurality of addresses in the logical-to-physical address translation map, wherein at least two of the plurality of logical indexes point to the at least one entry.
15. A method of controlling a data storage device comprising a volatile memory and a plurality of non-volatile memory devices comprising:
storing, in a volatile memory, a logical-to-physical address translation map that contains at least one entry that merges at least two addresses that map, to at least two physical locations of a plurality of memory devices; and
encoding the at least one entry with an error correcting code with a memory controller, wherein the error-correcting code is configured to operate as address data of the at least two physical locations.
16. The method according to claim 15 , further comprising:
receiving, at the memory controller, data containing the at least one entry; and
decoding, by the memory controller, data contained in the at least one entry in order to determine at least one of the at least two physical locations of a plurality of memory devices.
17. The method according to claim 16 , wherein the decoding step further comprising:
configuring the memory controller to determine a bit-size of one of the at least two addresses; and
configuring the memory controller to determine a i) bit size and ii) parity format of the error correcting code, wherein the decoding step is based on the configuring steps.
18. The method according to claim 15 , wherein, prior to merging, the at least two addresses of the at least one entry had a size of 32 bits, and wherein the at least one entry has a size of 33 bits.
19. The method according to claim 18 , wherein the error-correcting code is 8-bits in size.
20. A method of controlling a data storage device comprising a memory and a plurality of non-volatile memory devices comprising:
storing, in a volatile memory, a logical-to-physical address translation map that contains at least one entry to a physical location of a plurality of memory devices; and
encoding the at least one entry with an error correcting code with a memory controller,
wherein at least one bit of the error correcting code is configured by the memory controller to operate as address data, in the at least one entry, of the physical location of a plurality of memory devices.
21. A data storage device comprising a memory and a plurality of non-volatile memory devices:
means for configuring, in a volatile memory, a logical-to-physical address translation map that contains at least one entry to a physical location of a plurality of memory devices; and
means for encoding the at least one entry with an error correcting code,
wherein at least one bit of the error correcting code is configured by the configuring means to operate as address data, in the at least one entry, of the physical location of a plurality of memory devices.
22. The data storage device according to claim 21 , further comprising:
means for merging i) the at least one entry and ii) another entry pointing to another physical location of the plurality of memory devices into a single entry in the logical-to-physical address translation map,
wherein the encoding means encode the merged entry with the error correcting code,
wherein the merged entry contains address data for the physical location and the another physical location of the plurality of memory devices, and
wherein the error correcting code is a single error correcting code word.