Fast storage class memory using write once memory coding
View Patent ↗A memory with asymmetric command latency characteristics for WRITE operations utilizing WOM coding methodologies to reduce programming latency across a number of WRITE operations.
1. A solid state drive comprising:
a memory comprising asymmetric command latency characteristics for WRITE operations comprising data;
logic to direct the WRITE operations to memory sectors to which WOM coding is applied, based on the data satisfying a compression threshold level and a memory latency performance improvement target for the WRITE operations.
2. The solid state drive of claim 1 , wherein the WOM coding is configured to minimize a number of SET operations needed program the data in the memory.
3. The solid state drive of claim 1 , further comprising logic to allocate a size of the memory sectors based on an overprovisioning requirement associated with the memory latency performance improvement target.
4. The solid state drive of claim 1 , further comprising logic to direct the WRITE operations to the memory sectors on condition that the data has a compressibility ratio satisfying a configured threshold level.
5. The solid state drive of claim 4 , further comprising logic to allocate a dedicated memory partition to which to apply the WOM coding.
6. The solid state drive of claim 1 , further comprising logic to:
direct the WRITE operations to the memory sectors based on a comparison of a compressibility ratio of the data and an overprovisioning requirement of the WOM coding.
7. The solid state drive of claim 6 , further comprising logic to apply compression to the data before shaping the data for the WOM coding.
8. The solid state drive of claim 7 , further comprising logic to direct the WRITE operations to particular memory sectors based on a comparison of the overprovisioning requirement and a data size reduction obtained by applying compression to the data.
9. An apparatus comprising:
a memory comprising asymmetric command latency characteristics for WRITE operations comprising data; and
a controller configured to:
apply WOM coding when writing the data based on the data satisfying a compression threshold level; and
otherwise not apply the WOM coding.
10. The apparatus of claim 9 , the controller further configured to allocate memory sectors for the WRITE operation based on a compression efficiency of the data.
11. The apparatus of claim 10 , the controller further configured to direct the WRITE operations to the memory sectors on condition that the data has a compressibility ratio satisfying the compression threshold level.
12. The apparatus of claim 11 , the controller further configured to apply compression to the data, followed by data shaping.
13. The apparatus of claim 9 , the controller further configured to direct the WRITE operations to particular memory sectors based on a performance improvement target for the data.
14. The apparatus of claim 13 , wherein the memory is a phase change memory.
15. The apparatus of claim 9 , the controller further configured to direct the WRITE operations to particular memory sectors based on a comparison of an overprovisioning requirement and a data size reduction obtained by applying compression to the data.
16. A memory device comprising:
asymmetric command latency memory means; and
means to apply WOM coding to configured memory sectors of the memory means based on the data satisfying a compression threshold level and a memory latency performance improvement target for WRITE operations.
17. The memory device of claim 16 , further comprising means to allocate a size of the memory sectors based on an overprovisioning requirement associated with the memory latency performance improvement target.
18. The memory device of claim 16 , further comprising means to direct the WRITE operations to the memory sectors on condition that data of the WRITE operations has a compressibility ratio satisfying a configured threshold level.
19. The memory device of claim 16 , further comprising means to allocate the memory sectors for the WRITE operations based on a compression efficiency of data of the WRITE operations.
20. The memory device of claim 16 , further comprising means to apply compression to data of the WRITE operations, followed by data shaping.