IP Library Granted Patent US 11,756,932
Granted Patent B2
US 11,756,932 · App. 17/107,838 · Granted Sep 12, 2023

Sloped interconnector for stacked die package

Inventors: Xianlu Cui (Shanghai, CN); Junrong Yan (Shanghai, CN); Cheekeong Chin (Shanghai, CN); Zhonghua Qian (Shanghai, CN)
Assignee: SANDISK TECHNOLOGIES LLC
H01L25/0657H01L23/562H01L25/50H01L2225/06506H01L2225/06517H01L2225/06548H01L2225/06562H01L2225/06572H01L2225/06582
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Quick Facts
Patent No.
US 11,756,932
App. No.
17/107,838
Granted
Sep 12, 2023
Kind
B2
Abstract

A semiconductor device package includes a mechanical support structure that provides mechanical support to a stack of dies, where the dies are laterally offset from each other. The support structure has a sloped surface that is disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure. Electrical contacts are disposed on the sloped surface of the mechanical support structure for electrically interfacing with the stacked dies and on a different surface of the mechanical support structure for electrically interfacing with a substrate.

Claims (27)

1. An apparatus, comprising:

a mechanical support structure for supporting a plurality of integrated circuit dies, the mechanical support structure comprising a structure that is separate from the plurality of integrated circuit dies, the plurality of integrated circuit dies selectively coupled to the mechanical support structure;

a sloped surface of the mechanical support structure, the sloped surface disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanical support structure; and

a plurality of first electrical contacts disposed on the sloped surface of the mechanical support structure for electrically interfacing with the plurality of integrated circuit dies,

wherein the plurality of integrated circuit dies are stacked and laterally offset relative to each other such that a plurality of device electrical contacts along edges of the plurality of integrated circuit dies are aligned to interface with the plurality of first electrical contacts disposed on the sloped surface of the mechanical support structure, and

wherein the plurality of device electrical contacts comprise at least two rows of electrical contacts on a single integrated circuit die of the plurality of integrated circuit dies, the at least two rows of electrical contacts have different heights, and the different heights are selected to compensate for the non-perpendicular and non-parallel angle of the sloped surface of the mechanical support structure.

2. The apparatus of claim 1 , wherein at least one row of the at least two rows of electrical contacts comprises conductive pillars.

3. The apparatus of claim 1 , further comprising:

a substrate upon which the mechanical support structure is mounted; and

a second plurality of electrical contacts disposed on a different surface of the mechanical support structure for electrically interfacing with the substrate, thereby enabling electrical communication between the substrate and the plurality of integrated circuit dies.

4. The apparatus of claim 3 , wherein the second plurality of electrical contacts are in electrical communication with the first plurality of electrical contacts such that the mechanical support structure provides electrical connections between the plurality of integrated circuit dies and the substrate.

5. The apparatus of claim 4 , further comprising a plurality of through-silicon-vias disposed within the mechanical support structure between the sloped surface and the different surface, the through-silicon-vias providing the electrical communication between the first and second pluralities of electrical contacts.

6. The apparatus of claim 3 , further comprising a plurality of electrical traces disposed in one or more of the sloped surface and the different surface providing electrical communications between the first and second pluralities of electrical contacts.

7. The apparatus of claim 6 , wherein at least a portion of the plurality of electrical traces comprise a redistribution layer making at least a portion of the first and second pluralities of electrical contacts available in another location on the mechanical support structure.

8. The apparatus of claim 3 , further comprising a spacer disposed between the plurality of stacked integrated circuit dies and the substrate, the spacer providing mechanical support to the plurality of integrated circuit dies and aligning the plurality of integrated circuit dies with the first plurality of electrical contacts.

9. The apparatus of claim 1 , further comprising an encapsulation material formed around both the plurality of integrated circuit dies and the mechanical support structure.

10. The apparatus of claim 1 , further comprising a plurality of electrical interconnects between the plurality of integrated circuit dies.

11. The apparatus of claim 1 , wherein the sloped surface comprises a plurality of steps and an overall angle of the plurality of steps comprises the non-perpendicular and non-parallel angle of the sloped surface with regard to the other surfaces of the mechanical support structure.

12. The apparatus of claim 1 , wherein the mechanical support structure comprises an insulator, the insulator comprising one or more of silicon, glass, ceramic, and polycrystalline silicon.

13. An apparatus, comprising:

means for mechanically supporting a plurality of laterally offset, stacked, integrated circuit devices, the means comprising a structure that is separate from the plurality of integrated circuit devices, the plurality of laterally offset, stacked, integrated circuit devices selectively coupled to the structure;

means for providing electrical communication between integrated circuit device electrical contacts along stacked, overhanging edges of the plurality of laterally offset, stacked, integrated circuit devices and a substrate through the means for mechanically supporting the plurality of laterally offset, stacked, integrated circuit devices;

a sloped surface of the mechanically supporting means, the sloped surface disposed at a non-perpendicular and non-parallel angle to other surfaces of the mechanically support means; and

a plurality of first electrical contacts disposed on the sloped surface of the mechanically supporting means for electrically interfacing with the plurality of laterally offset, stacked, integrated circuit devices,

wherein the plurality of laterally offset, stacked, integrated circuit devices are stacked and laterally offset relative to each other such that a plurality of device electrical contacts along edges of the plurality of laterally offset, stacked, integrated circuit devices are aligned to interface with the plurality of first electrical contacts disposed on the sloped surface of the mechanically supporting means, and

wherein the plurality of device electrical contacts comprise at least two rows of electrical contacts on a single integrated circuit device of the plurality of laterally offset, stacked, integrated circuit devices, the at least two rows of electrical contacts have different heights, and the different heights are selected to compensate for the non-perpendicular and non-parallel angle of the sloped surface of the mechanically supporting means.

14. The apparatus of claim 13 , further comprising means for compensating for a non-perpendicular and non-parallel angle of the means for mechanically supporting the plurality of laterally offset, stacked, integrated circuit devices in order to provide the electrical communication between the integrated circuit device electrical contacts and the substrate.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2021
From: CUI, XIANLU; YAN, JUNRONG; CHIN, CHEECKEONG; QIAN, ZHONGHUA
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 055004/0232 →
Priority Claims (1)
CN 202010619593.5 · Jun 30, 2020 · national
Continuity (1)
Related Publication 20210407967A1 · Dec 30, 2021