Methods of communicating to different types of memory modules in a memory channel
View Patent ↗A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.
1. A method of communicating to different types of memory modules in a memory channel, the method comprising:
initializing a programmable heterogeneous memory controller to each memory module coupled to a memory channel bus;
adapting each pin of a memory channel interface to communicate over wire interconnect of the memory channel bus to respective pins of each memory module in response to a differing pinout for each different type of memory module being accessed;
generating logic signals for communication over the wire interconnect of the memory channel bus to each memory module in response to differing signal levels for each different type of memory module being accessed;
wherein the logic signals are generated on the wire interconnect of the memory channel bus with appropriate signal timing to communicate with each memory module in further response to differing signal timing for each different type of memory module being accessed; and
wherein address and control signal lines are used in a different manner to address additional memory to increase memory capacity.
2. The method of claim 1 , further comprising:
loading into the heterogeneous memory controller one or more memory module software drivers associated with the type of memory modules being accessed.
3. The method of claim 2 , further comprising:
downloading at least one of the one or more memory module software drivers over a network.
4. The method of claim 2 , wherein
in response to each different type of memory module being accessed, the one or more memory module software drivers each include information regarding the respective pins of the memory module, logic signals to communicate with the memory module, and signal timing to communicate with the memory module.
5. The method of claim 1 , wherein
the adapting of each pin includes
assigning additional functionality to underused or unused pins so that a communication protocol between one or more memory modules and the programmable heterogeneous memory controller may be extended.
6. The method of claim 5 , wherein
a feedback pin is defined so that the programmable heterogeneous memory controller can receive status information from the memory module.
7. The method of claim 1 , wherein
the generating of logic signals includes
generating active high logic signals or active low logic signals in response to the type of memory module being accessed.
8. The method of claim 1 , wherein
the initializing of the programmable heterogeneous memory controller includes
polling each socket in the memory channel for a memory module;
reading a memory module identification from each memory module to determine the type of memory module coupled into each socket; and
loading a memory module software driver into the programmable heterogeneous memory controller for each different type of memory module coupled into the memory channel.
9. The method of claim 8 , wherein
the initializing of the programmable heterogeneous memory controller further includes
storing each memory module identifier associated with each socket into the programmable heterogeneous memory controller.
10. The method of claim 9 , wherein
the initializing of the programmable heterogeneous memory controller further includes
loading a state machine with the memory module software driver to access the memory module in a given socket.
11. A method of communicating to different types of memory modules in a memory channel, the method comprising:
initializing a programmable heterogeneous memory controller to each memory module coupled to a memory channel bus;
adapting each pin of a memory channel interface to communicate over wire interconnect of the memory channel bus to respective pins of each memory module in response to each different type of memory module being accessed;
utilizing pre-existing address pins over multiple cycles to form a larger address to address additional memory and increase memory capacity;
generating logic signals for communication over the wire interconnect of the memory channel bus to each memory module in response to each different type of memory module being accessed; and
wherein the logic signals are generated on the wire interconnect of the memory channel bus with appropriate signal timing to communicate with each memory module in response to each different type of memory module being accessed.
12. The method of claim 11 , wherein
the generating of logic signals includes
generating active high logic signals or active low logic signals in response to the type of memory module being accessed.
13. The method of claim 11 , wherein
the initializing of the programmable heterogeneous memory controller includes
polling each socket in the memory channel for a memory module;
reading a memory module identification from each memory module to determine the type of memory module coupled into each socket; and
loading a memory module software driver into the programmable heterogeneous memory controller for each different type of memory module coupled into the memory channel.
14. The method of claim 13 , wherein
the initializing of the programmable heterogeneous memory controller further includes
storing each memory module identifier associated with each socket into the programmable heterogeneous memory controller.
15. The method of claim 14 , wherein
the initializing of the programmable heterogeneous memory controller further includes
loading a state machine with the memory module software driver to access the memory module in a given socket.