IP Library Granted Patent US 11,488,684
Granted Patent B1
US 11,488,684 · App. 17/352,953 · Granted Nov 1, 2022

Storage system and method for decision-based memory read threshold calibration

Inventors: Eran Sharon (Rishon Lezion, IL); Ran Zamir (Ramat Gan, IL); Alexander Bazarsky (Holon, IL)
Assignee: Western Digital Technologies, Inc.
G11C29/52G11C29/10G11C29/12005G11C29/42H03K19/018521H03K19/21G11C2029/1202G11C2207/2254
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Quick Facts
Patent No.
US 11,488,684
App. No.
17/352,953
Granted
Nov 1, 2022
Kind
B1
Abstract

A read threshold voltage can vary over time due to process variation, data retention issues, and program disturb conditions. A storage system can calibrate the read threshold voltage using data from a decoded codeword read from a wordline in the memory. For example, the storage system can use the data instead of syndrome weight in a bit error rate estimate scan (BES). As another example, the storage system can use the data to generate a bit error rate distribution, which can be used instead of a cell voltage distribution histogram. Using these techniques can help reduce latency and power consumption, increase throughput, and improve quality of service.

Claims (40)

1. A storage system comprising:

a memory; and

a controller coupled to the memory and configured to:

decode a codeword read from a wordline in the memory;

determine that a bit error rate in the decoded codeword is above a threshold; and

in response to determining that the bit error rate in the decoded codeword is above the threshold:

designate the wordline as a candidate for read threshold calibration;

store data from the decoded codeword; and

cause read threshold calibration to be performed using the data from the decoded codeword instead of syndrome weight in a bit error rate estimate scan (BES).

2. The storage system of claim 1 , wherein the read threshold calibration is performed upon determining that the bit error rate is above the threshold.

3. The storage system of claim 1 , wherein the codeword is read during a sequential read operation.

4. The storage system of claim 1 , wherein the read threshold calibration is performed during a maintenance operation.

5. The storage system of claim 1 , wherein the data from the decoded codeword is stored in the controller.

6. The storage system of claim 1 , wherein the data from the decoded codeword is stored in a complementary metal-oxide-semiconductor (CMOS) bonded array (CBA).

7. The storage system of claim 1 , wherein the codeword is read during a maintenance operation.

8. The storage system of claim 1 , wherein the read threshold calibration is performed in the memory.

9. The storage system of claim 1 , wherein the read threshold calibration is performed in a complementary metal-oxide-semiconductor (CMOS) bonded array (CBA).

10. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

11. In a storage system comprising a controller and a memory, a method comprising:

sending, from the controller to the memory, a decision-based valley search command for a wordline in the memory;

decoding a codeword read from the wordline;

passing data from the decoded codeword to latches in the memory;

reading the wordline;

generating a bit error rate distribution by performing an exclusive-or operation on data read from the wordline and the data from the decoded codeword; and

performing a read threshold calibration by finding minima in the bit error rate distribution.

12. The method of claim 11 , wherein the minima are found in the bit error rate distribution instead of a cell voltage distribution histogram.

13. The method of claim 11 , wherein the read threshold calibration is performed in the memory.

14. The method of claim 11 , wherein the read threshold calibration is performed in a complementary metal-oxide-semiconductor (CMOS) bonded array (CBA).

15. The method of claim 11 , wherein the data from the decoded codeword is stored in the controller.

16. The method of claim 11 , wherein the data from the decoded codeword is stored in a complementary metal-oxide-semiconductor (CMOS) bonded array (CBA).

17. The method of claim 11 , wherein the read threshold calibration comprises a valley search operation.

18. The method of claim 11 , further comprising sending a result of the read threshold calibration to a controller in the storage system.

19. A storage system comprising:

a memory;

means for decoding a codeword read from a wordline in the memory;

means for determining that a bit error rate in the decoded codeword is above a threshold; and

means for performing the following in response to determining that the bit error rate in the decoded codeword is above the threshold:

designating the wordline as a candidate for read threshold calibration;

storing data from the decoded codeword; and

causing read threshold calibration to be performed using the data from the decoded codeword instead of syndrome weight in a bit error rate estimate scan (BES).

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 057651 FRAME 0296 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058981/0958 →
SECURITY INTEREST Recorded Sep 17, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 057651/0296 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2021
From: SHARON, ERAN; ZAMIR, RAN; BAZARSKY, ALEXANDER
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 056605/0222 →