Staged-backup flash backed dram module
View Patent ↗A memory device for use with a primary power source includes: volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state; an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source; a non-volatile memory; and a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into a normal operating state and the memory portions from which data is not being moved into a low-power state.
1. A memory device for use with a primary power source, said memory device comprising:
volatile memory including a plurality of memory portions each of which has a normal operating state and a low-power state;
an interface for connecting to a backup power source arranged to temporarily power the volatile memory upon a loss of power from the primary power source;
a non-volatile memory; and
a controller in communication with the volatile memory and the non-volatile memory programmed to detect a loss of power of the primary power source and in response to move data from the volatile memory to the non-volatile memory at least one memory portion at a time, and while moving data from the volatile memory to the non-volatile memory place the memory portions from which data is being moved into the normal operating state and the memory portions from which data is not being moved into the low-power state.
2. The memory device of claim 1 , further comprising a device-ready output and wherein the controller is further programmed to:
(a) determine whether the backup power source has sufficient power to power the memory device during the move of data from the volatile memory to the non-volatile memory;
(b) determine whether the non-volatile memory is prepared to accept the data stored in the volatile memory; and
based on (a) and (b), drive the device ready output.
3. The memory device of claim 1 , wherein the moving of data from the volatile memory to the non-volatile memory and the controlling of the states of the portions is based on a rate which data can be moved into the non-volatile memory.
4. The memory device of claim 1 , wherein the volatile memory is a dynamic random access memory, the portions are dynamic random access memory chips, and the low-power state is self-refresh.
5. The memory device of claim 1 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).
6. The memory device of claim 1 , wherein the controller comprises at least one of an application-specific integrated circuit (ASIC) and a field programmable gate array (FPGA).
7. The memory device of claim 1 , wherein power from the backup power source is primarily from a capacitor.
8. The memory device of claim 1 , wherein power from the backup power source is primarily from a super capacitor.
9. The memory device of claim 1 , further comprising an output health signal and a state-of-health monitor that monitors the health of the backup power source and causes the output health signal to be driven if the backup source has insufficient power to provide backup power.
10. The memory device of claim 1 , wherein the controller is further programmed to detect a restoration of power of the primary power source and in response move data from the non-volatile memory to the volatile memory.
11. The memory device of claim 1 , where in the non-volatile memory comprises four flash memory chips.
12. A method comprising:
detecting a power failure of a primary power source of a volatile memory comprising a plurality of memory portions each of which has a normal operating state and a low-power state; and
in response to detecting the power failure and while the volatile memory is powered by a backup power source:
moving data stored in the volatile memory to a non-volatile memory at least one memory portion at a time; and
while moving data from the volatile memory to the non-volatile memory, placing memory portions from which data is being moved into the normal operating state and memory portions from which is not being moved into the low-power state.
13. The method of claim 12 , further comprising:
(a) determining whether the backup power source has sufficient power to power the volatile memory during the move of data from the volatile memory to the non-volatile memory;
(b) determining whether the non-volatile memory is prepared to accept the data stored in the volatile memory; and
based on (a) and (b), driving a device ready output.
14. The method of claim 12 , wherein the moving of data from the volatile memory to the non-volatile memory and the controlling of the states of the portions is based on a rate which data can be moved into the non-volatile memory.
15. The method of claim 12 , wherein the volatile memory is a dynamic random access memory, the portions are dynamic random access memory chips, and the low-power state is self-refresh.
16. The method of claim 12 , wherein the non-volatile memory comprises electrically erasable programmable read-only memories (EEPROMs).
17. The method of claim 12 , wherein power from the backup power source is primarily from a capacitor.
18. The method of claim 12 , wherein power from the backup power source is primarily from a super capacitor.
19. The method of claim 12 , further comprising:
monitoring the health of the backup power source; and
driving an output health signal if the backup source has insufficient power to provide backup power.
20. The method of claim 12 , further comprising:
detecting a restoration of power of the primary power source; and
in response, moving data from the non-volatile memory to the volatile memory.