IP Library Granted Patent US 11,924,964
Granted Patent B2
US 11,924,964 · App. 17/715,673 · Granted Mar 5, 2024

Printed circuit board for galvanic effect reduction

Inventors: Lin Hui Chen (Taichung, TW); Songtao Lu (Shanghai, CN); Chien Te Chen (Taichung, TW); Yu Ying Tan (Taichung, TW); Huang Pao Yi (Taichung, TW); Ching Chuan Hsieh (Taichung, TW); T. Sharanya Kaminda (Bengaluru, IN); Chia-Hsuan Huang (Huang, TW)
Assignee: Western Digital Technologies, Inc.
H05K1/0218H05K1/116H05K2201/09381H05K2201/0939
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,924,964
App. No.
17/715,673
Granted
Mar 5, 2024
Kind
B2
Abstract

Devices and methods are described for reducing etching due to Galvanic Effect within a printed circuit board (PCB) that may be used in an electronic device. Specifically, a contact trace is coupled to a contact finger that has a substantially larger surface area than the contact trace. The contact finger is configured to couple the electronic device to a host device. The contact trace is electrically isolated from the rest of the PCB circuitry during a fabrication process by a separation distance between an exposed portion of the contact trace and an impedance trace. The contact finger and the exposed portion of the contact trace are plated with a common material to reduce galvanic etching of the contact trace during fabrication. The contact trace is then connected to the impedance trace using a solder joint.

Claims (37)

1. A printed circuit board for an electronic device, comprising:

a substrate having a first side and a second side opposite to the first side;

a contact finger disposed on the first side of the substrate configured to interface with an external electronic device;

a contact trace coupled to the contact finger and extending from the first side of the substrate to the second side of the substrate, wherein the contact trace has an exposed portion disposed on the second side of the substrate in the form of a via connection pad; and

an impedance trace disposed on the second side of the substrate and configured to be coupled to one or more components of the electronic device;

an outer pad coupled to the impedance trace, wherein the outer pad surrounds the via connection pad and is electrically separated from the via connection pad by a separation distance;

wherein the contact finger and the via connection pad are plated with a common material to reduce galvanic etching of the contact trace; and

wherein the via connection pad of the contact trace is electrically connected to the impedance trace by way of a solder joint.

2. The printed circuit board of claim 1 , wherein the outer pad is plated with the common material.

3. The printed circuit board of claim 1 , wherein the separation distance separates the outer pad and the via connection pad by a distance of at least 15 μm.

4. The printed circuit board of claim 1 , wherein the via connection pad and the outer pad are circular.

5. The printed circuit board of claim 1 , wherein the via connection pad is a square shape and the outer pad is circular.

6. The printed circuit board of claim 1 , wherein the via connection pad and the outer pad are a square shape.

7. The printed circuit board of claim 1 , wherein the common material is gold.

8. The printed circuit board of claim 1 , wherein the common material is nickel-gold.

9. A method for reducing etching due to galvanic effect in a printed circuit board in an electronic device, the method comprising:

determining a ratio of a surface area of a contact finger to a surface area of an exposed portion of a contact trace electrically connected to the contact finger, wherein the contact finger is configured to provide an electrical connection to an external electronic device;

determining whether the ratio exceeds a predetermined threshold;

responsive to determining that the ratio exceeds the predetermined threshold, separating the exposed portion of the contact trace into a via connection pad and an outer connection pad configured to be coupled to an impedance trace, wherein the via connection pad and outer connection pad are physically separated by a separation distance;

plating the contact finger and the via connection pad with a common material; and

electrically connecting the via connection pad and the outer connection pad using a solder joint.

10. The method of claim 9 , wherein the outer pad is at least partially plated with the common material.

11. The method of claim 9 , wherein the separation distance separates the outer pad and the via connection pad by a distance of at least 15 μm.

12. The method of claim 9 , wherein the via connection pad and the outer pad are circular.

13. The method of claim 9 , wherein the via connection pad is a square shape and the outer pad is circular.

14. The method of claim 9 , wherein the common material is gold.

15. A card-type data storage device, comprising:

a substrate having a first side and a second side opposite to the first side;

a contact finger disposed on the first side of the substrate configured to interface with a host device and plated with a plating material;

a first trace coupled to the first contact finger and extending from the first side of the substrate to the second side of the substrate, wherein the first trace has an exposed portion disposed on the second side of the substrate in the form of a via connection pad, the via connection pad being plated with the plating material; and

a second trace disposed on the second side of the substrate and coupled to an outer pad, wherein the outer pad surrounds the via connection pad and is electrically separated from the via connection pad by a separation distance; and

wherein the via connection pad is electrically connected to the outer pad through a solder joint.

16. The card-type data storage device of claim 15 , outer pad is plated with the plating material.

17. The card-type data storage device of claim 15 , wherein the separation distance separates the outer pad and the via connection pad by a distance between 1 μm and 100 μm.

18. The card-type data storage device of claim 15 , wherein the via connection pad is a square shape and the outer pad is circular.

19. The card-type data storage device of claim 15 , wherein the via connection pad and the outer pad are circular.

20. The card-type data storage device of claim 15 , wherein the plating material is at least one of gold or nickel-gold.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2022
From: HUI CHEN, LIN; LU, SONGTAO; TE CHEN, CHIEN; TAN, YU YING; PAO YI, HUANG; HSIEH, CHING CHUAN; KAMINDA, T. SHARANYA; HUANG, CHIA-HSUAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059535/0602 →