IP Library Granted Patent US 11,940,908
Granted Patent B2
US 11,940,908 · App. 17/723,635 · Granted Mar 26, 2024

Relative size reduction of a logical-to-physical table

Inventors: Chinnakrishnan Ballapuram (San Jose, CA); Shay Benisty (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F12/0246G06F11/076G06F11/1064G06F12/0253G06F12/0864G06F12/0882G06F2212/7201
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Quick Facts
Patent No.
US 11,940,908
App. No.
17/723,635
Granted
Mar 26, 2024
Kind
B2
Abstract

A data storage device whose controller is configured to apply a hash function to a logical address specified in a received host request to obtain a first portion of the corresponding physical address (e.g., the channel number or channel and die numbers). This feature of the controller enables the L2P table stored in the DRAM associated with the controller to have physical-address entries that contain therein only complementary second portions of the physical addresses, but not the first portions. Such shorter physical-address entries in the L2P table enable a corresponding beneficial reduction in the size of the DRAM and can further be leveraged to have optimized and aligned access to the L2P table in the DRAM.

Claims (47)

1. A data storage device, comprising:

a non-volatile memory comprising a plurality of storage dies organized into two or more memory channels, each of the dies being organized into memory blocks and pages to store user data;

a volatile memory to store a logical-to-physical (L2P) table; and

a controller configured to:

receive a host request specifying a logical address;

compute a hash value by applying a hash function to the logical address, the hash value providing a first portion of a first physical address comprising a channel number corresponding to the logical address;

retrieve a second portion of the first physical address from the L2P table based on the logical address;

combine the first portion and the second portion to determine the first physical address; and

perform a memory operation based on the first physical address.

2. The data storage device of claim 1 ,

wherein the second portion comprises a block number and a page number corresponding to the logical address.

3. The data storage device of claim 1 , wherein the first portion further comprises a die number corresponding to the logical address.

4. The data storage device of claim 3 , wherein the first portion consists of the channel number and the die number.

5. The data storage device of claim 1 , wherein the first portion consists of the channel number.

6. The data storage device of claim 2 , wherein the second portion further comprises a die number corresponding to the logical address.

7. The data storage device of claim 6 , wherein the second portion consists of the die number, the block number, and the channel number.

8. The data storage device of claim 2 , wherein the second portion consists of the block number and the page number.

9. The data storage device of claim 1 , wherein the L2P table does not have channel numbers stored therein.

10. The data storage device of claim 1 , wherein the controller is configured to combine the first portion and the second portion by concatenating the first portion and the second portion.

11. The data storage device of claim 1 , wherein the controller is configured to perform a next write operation involving the logical address by writing to a different second physical address in the non-volatile memory, each of the first physical address and the second physical address including the hash value in the first portion thereof.

12. The data storage device of claim 1 , wherein the controller is configured to perform garbage collection, the garbage collection including moving valid user data from the first physical address to a different second physical address in the non-volatile memory, each of the first physical address and the second physical address including the hash value in the first portion thereof.

13. The data storage device of claim 1 , wherein the controller is configured to:

retrieve the second portion from the volatile memory together with a corresponding error-correction-code (ECC) portion stored therein; and

check for errors in the second portion using the ECC portion.

14. The data storage device of claim 13 ,

wherein an ECC overhead associated with storage of the ECC portion in the volatile memory is less than 5%; and

wherein the first physical address has a length of more than 32 bits.

15. A method of processing host requests in a data storage device comprising a non-volatile memory to store user data and a volatile memory to store a logical- to-physical (L2P) table, the method comprising:

receiving a host request including a logical address;

computing a hash value by applying a hash function to the logical address, the hash value providing a first portion of a first physical address in the non-volatile memory, the non-volatile memory including a plurality of storage dies organized into two or more memory channels, each of the dies being organized into memory blocks and pages to store user data the first portion including a channel number corresponding to the logical address;

retrieving a second portion of the first physical address from the L2P table based on the logical address;

combining the first portion and the second portion to determine the first physical address; and

performing a memory operation based on the first physical address.

16. The method of claim 15 , wherein the combining comprises concatenating the first portion and the second portion.

17. The method of claim 15 , further comprising performing a next write operation involving the logical address by writing to a different second physical address in the non-volatile memory, each of the first physical address and the second physical address including the hash value in the first portion thereof.

18. The method of claim 15 , further comprising performing garbage collection, the garbage collection including moving valid user data from the first physical address to a different second physical address in the non-volatile memory, each of the first physical address and the second physical address including the hash value in the first portion thereof.

19. The method of claim 15 , further comprising:

retrieving the second portion from the volatile memory together with a corresponding error-correction-code (ECC) portion stored therein; and

checking for errors in the second portion using the ECC portion.

20. An apparatus, comprising:

non-volatile memory means for storing user data including a plurality of storage dies organized into two or more memory channels, each of the dies being organized into memory blocks and pages;

volatile memory means for storing a logical-to-physical (L2P) table;

means for receiving a host request including a logical address;

means for computing a hash value by applying a hash function to the logical address, the hash value providing a first portion of a first physical address including a channel number corresponding to the logical address;

means for retrieving a second portion of the first physical address from the L2P table based on the logical address;

means for combining the first portion and the second portion to determine the first physical address; and

means for performing a memory operation in the non-volatile memory means based on the first physical address.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 19, 2022
From: BALLAPURAM, CHINNAKRISHNAN; BENISTY, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059634/0026 →